MK50H28 datasheet(24/64 Pages) STMICROELECTRONICS

24 / 64 page

4.1.2.5 Control and Status Register 4 (CSR4)

CSR4 allows redefinition of the bus master interface.

RAP<3:1> = 4

BIT

NAME

DESCRIPTION

15:12

XWD0/1,

RWD0/1

Watchdog Timers. These bits enable and determine the timer values for the Transmit and

Receive Watchdog Timers. These timers are independently programmable and are reset

by any transition on the TCLK and RCLK pins respectively. The watchdog timers will

expire after approximately Wn SYSCLK cycles (if not reset by transition on TCLK/RCLK)

and Provider Primitive 3 will be issued. The following table shows the selections for Wn:

Reserved, must be written as zero.

XHOLD

Setting this bit enables the Transmit FIFO Hold-Off mechanism of the MK50H28. If

XHOLD=1 and the Transmit FIFO is emplty, the MK50H28 transmitter will be ”held off”

from transmitting a frame until the FIFO has at least the XHOLD Watermark (selected

with FWM below) of data, or the entire frame , in the Transmit FIFO.

09:08

FWM

These bits define the FIFO watermarks. FIFO watermarks prevent the MK50H28 from

performing DMA transfers to/from the data buffers until the FIFOs contain a minimum

amount of data or space for data. For receive, data will only be transferred to the buffers

after the receive FIFO has at least N 16-bit words or end of frame has been received.

Conversely, for transmit, data will only be transferred from the data buffers when the

transmit FIFO has room for at least N words of data. The Transmit Hold-Off Watermark

enabled by setting XHOLD=1 is also defined by these bits. N is defined as follows:

* Suggested setting

BAE

Bus Address Enable: if BAE is set then the A23-A20 pins are driven by the MK50H28

constantly providing the ability to use A23-A20 for memory bus selection. If clear, A23-

A20 behave identically to A19- A16.

BUSR

If this bit is set, pin 15 becomes input BUSREL. If this bit is clear then pin 15 is either

BM0 or BYTE depending on bit 00. For more information see the description for pin 15

in this document. BUSR is READ/WRITE and cleared on bus Reset.

XWD1/RWD1

XWD0/RWD0

Disabled

FWM <1:0>

FWM N

XHOLD N

Not Allowed

10*

9 words

19 Words

17 words

11 Words

25 words

3 Words

MK50H28

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