MK50H28 datasheet(25/64 Pages) STMICROELECTRONICS

25 / 64 page

BIT

NAME

DESCRIPTION

BSWPC

This bit determines the byte ordering of all ”non-data” DMA transfers. This transfers

refers to any DMA transfers that access memory other than the data buffers themselves.

This includes the Initialization Block, Descriptors, and Status Buffer. It has no effect on

data DMAtransfers. BSWPC allows the MK50H28 to operate with memory organizations

that have bits 07:00 at even addresses and with bits 15:08 at odd addressses or vice

versa. BSWPC is Read/Write and cleared by BUS RESET.

With BSWPC = 0:

Address

With BSWPC = 1:

Address

04:03

BURST

This field determines the maximum number of data transfers performed each time control

of the host bus is obtained. BURST is READ/WRITE and cleared on bus Reset.

*Suggested setting

BSWPD

This bit determines the byte ordering of all data DMA transfers. Data transfers are

those to or from a data buffer. BSWPD has no effect on non-data transfers. The effect

of BSWPD on data transfers is the same as that of BSWPC on non-data transfers

(see above). For most applications, including most 68000 based systems, this bit

should be set.

ACON

ALE CONTROL defines the assertive state of pin 18 when the MK50H28 is a Bus

Master. ACON is READ/ WRITE and cleared by Bus RESET.

BCON

BYTE CONTROL redefines the Byte Mask and Hold I/O pins. BCON is READ/WRITE

and cleared by Bus RESET.

XX0

. . .

8. . .

XX1

8. . .

XX0

XX1

. . .

BURST <1:0>

8 bit mode

16 bit mode

10*

unlimited

ACON

PIN18

NAME

ASSERTED HIGH

ALE

ASSERTED LOW

BCON

PIN16

PIN15

PIN17

BM1

BM0

HOLD

BUSAKO

BYTE

BUSRQ

MK50H28

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