MK50H28 datasheet(43/64 Pages) STMICROELECTRONICS

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4.3.2.3 Transmit Message Descriptor 1 (TMD1)

TBADR<15:00>

BIT

NAME

DESCRIPTION

15:00

TBADR

The Low Order 16 address bits of the buffer pointed to by this descriptor. TBADR is

written by the Host and unchanged by MK50H28. The least significant bit is zero since

the descriptor must be word aligned.

4.3.2.4 Transmit Message Descriptor 2 (TMD2)

BIT

NAME

DESCRIPTION

15:00

BCNT

Buffer Byte Count is the usable lenght of the buffer pointed to by this descriptor

expressed in two’s complement. Thiis field is not used by the MK50H28.

BCNT<15:00>

BIT

NAME

DESCRIPTION

11:09

LMI Frame

Type to be

Transmitted

These bits define the type of frame to be transmitted when transmission occurs due to

LMI polling (enabled by UPRIM 8 with UPARM=2 - see 4.1.2.2).

Bit Encoding (MSB - LSB)

Frame Type

000

SVC Frame or Transparent Mode frame

001

Reserved

010

Full Status Enquiry frame

011

Status Enquiry frame (LIV only)

100

Asynchronous Status Frame

101

Update Status frame

110

Full Status frame

111

Status frame (LIV only)

11:09

Reserved. Must be written as zero.

TINTD

Transmit Interrupt Disable. If this bit is set, no transmit interrupt is generated when

ownership of this descriptor is released back to the host.

07:00

TBADR

The High Order 8 address bits of the buffer pointed to by this descriptor.

This field is written by the Host and unchanged by MK50H28.

MK50H28

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