MK50H28 datasheet(28/64 Pages) STMICROELECTRONICS

28 / 64 page

4.2.1 Mode Register

The Mode Register allows alteration of the MK50H28’s operating parameters.

LBACK

<2:0>

MFS

<4:0>

IADR + 00

0000

BIT

NAME

DESCRIPTION

15:11

MFS<4:0>

Minimum Frame Spacing defines the minimum number of flag sequences transmitted

between adjacent frames transmitted by the MK50H28. This only affects frames

transmitted by the MK50H28 and does not restrict the spacing of the

frames received by the MK50H28.

When using RTS/CTS control this field defines

the number of flags transmitted at the beginning of the frame after CTS is driven

low (minus one for the trailing flag). See the following table for encoding of this field.

10:06

Reserved. Must be written as zeros.

DRFCS

Disable Receiver FCS (CRC). When DRFCS = 0, the receiver will extract and check the

FCS field at the end of each frame. When DRFCS = 1, the receiver continues to extract

the last 16 or 32 bits of each frame, depending on FCSS, but no check is performed to

determine whether the FCS is correct. If the received frame is an even number of

bytes, the first 16 bits of the FCS will be appended to the end (as indicated by MCNT) of

the receive buffer data.

DTFCS

Disable Transmitter FCS. When DTFCS=0, the transmitter will generate and append the

FCS to each signal unit. When DTFCS = 1, the FCS logic is disabled, and no FCS is

generated with transmitted frames. Setting DTFCS = 1 is useful in loopback testing for

checking the ability of the receiver to detect an incorrect FCS.

FCSS

FCS Select. When FCSS = 1, a 16-bit FCS is selected otherwise a 32-bit FCS is used.

NUMBER OF FLAGS

MFS<4:0>

NUMBER OF FLAGS

MFS<4:0>

MK50H28

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