R5F2L3ACBNFP datasheet(105/848 Pages) RENESAS

105 / 848 page

6. Voltage Detection Circuit

REJ09B0441-0010 Rev.0.10

Jul 30, 2008

Page 69 of 809

Under development Preliminary specification

Specifications in this manual are tentative and subject to change.

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,

R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

6.2.7

Voltage Monitor 1 Circuit Control Register (VW1C)

Notes:

1. The VW1C0 is enabled when the VCA26 bit in the VCA2 register is set to 1 (voltage detection 1 circuit enabled).

Set the VW1C0 bit to 0 (disabled) when the VCA26 bit is set to 0 (voltage detection 1 circuit disabled).

To set the VW0C0 bit to 1 (enabled), follow the procedure shown in Table 6.4 Procedure for Setting Bits

Associated with Voltage Monitor 1 Interrupt.

2. To use the voltage monitor 1 interrupt to exit stop mode and to return again, write 0 and then 1 to the VW1C1 bit.

3. Bits VW1C2 and VW1C3 are enabled when the VCA26 bit in the VCA2 register is set to 1 (voltage detection 1

circuit enabled).

4. Set the VW1C2 bit to 0 by a program. When 0 is written by a program, this bit is set to 0 (and remains unchanged

even if 1 is written to it).

5. The VW1C7 bit is enabled when the VCAC1 bit in the VCAC register is set to 0 (one edge). After setting the

VCAC1 bit to 0, set the VW1C7 bit.

Set the PRC3 bit in the PRCR register to 1 (write enabled) before writing the VW1C register.

Rewriting the VW1C register may set the VW1C2 bit to 1. Set the VW1C2 bit to 0 after rewriting the VW1C

Address 0039h

Bit

b7b6

b5b4b3b2

Symbol

VW1C7

—

VW1F1

VW1F0

VW1C3

VW1C2

VW1C1

VW1C0

After Reset

000

1010

Bit

Symbol

Bit Name

Function

R/W

VW1C0 Voltage monitor 1 reset enable bit (1)

0: Disabled

1: Enabled

R/W

VW1C1 Voltage monitor 0 digital filter

disable mode select bit (2)

0: Digital filter enabled mode

(digital filter circuit enabled)

1: Digital filter disable mode

(digital filter circuit disabled)

R/W

VW1C2 Voltage change detection flag (3, 4)

0: Not detected

1: Vdet1 passing detected

R/W

VW1C3 Voltage detection 1 signal monitor flag (3) 0: VCC < Vdet1

1: VCC

≥ Vdet1

or voltage detection 1 circuit disabled

VW1F0 Sampling clock select bit

b5 b4

0 0: fOCO-S divided by 1

0 1: fOCO-S divided by 2

1 0: fOCO-S divided by 4

1 1: fOCO-S divided by 8

R/W

VW1F1

R/W

—

Reserved bit

Set to 0.

R/W

VW1C7 Voltage monitor 1 reset

generation condition select bit (5)

0: When VCC reaches Vdet1 or above.

1: When VCC reaches Vdet1 or below.

R/W

R5F2L3ACBNFP Datasheet(PDF) 105 Page - Renesas Technology Corp

R5F2L3ACBNFP Datasheet(HTML) 105 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL