R5F2L3ACBNFP datasheet(109/848 Pages) RENESAS

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6. Voltage Detection Circuit

REJ09B0441-0010 Rev.0.10

Jul 30, 2008

Page 73 of 809

Under development Preliminary specification

Specifications in this manual are tentative and subject to change.

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,

R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

6.4

Voltage Monitor 0 Reset

Table 6.3 lists the Procedure for Setting Bits Associated with Voltage Monitor 0 Reset and Figure 6.5 shows an

Operating Example of Voltage Monitor 0 Reset.

To use the voltage monitor 0 reset to exit stop mode, set the VW0C1 bit in the VW0C register to 1 (digital filter

disabled).

Note:

1. When the VW0C0 bit is set to 0, steps 3 and 4 can be executed simultaneously (with one instruction).

Figure 6.5

Operating Example of Voltage Monitor 0 Reset

Table 6.3

Procedure for Setting Bits Associated with Voltage Monitor 0 Reset

Step

When Using Digital Filter

When Using No Digital Filter

Set the VCA25 bit in the VCA2 register to 1 (voltage detection 0 circuit enabled).

Wait for td(E-A).

Select the sampling clock of the digital filter by

bits VW0F1 to VW0F0 in the VW0C register.

Set the VW0C7 bit in the VW0C register to 1.

4 (1)

Set the VW0C1 bit in the VW0C register to 0

(digital filter enabled).

Set the VW0C1 bit in the VW0C register to 1

(digital filter disabled).

Set the VW0C2 bit in the VW0C register to 0.

Set the CM14 bit in the CM1 register to 0

(low-speed on-chip oscillator on).

−

Wait for 4 cycles of the sampling clock of

the digital filter.

− (No wait time required)

Set the VW0C0 bit in the VW0C register to 1 (voltage monitor 0 reset enabled).

Vdet0

Internal reset signal

VCC

The above applies under the following conditions:

• VCA25 bit in VCA2 register = 1 (voltage detection 0 circuit enabled)

• VW0C0 bit in VW0C register = 1 (voltage monitor 0 reset enabled)

When the internal reset signal is driven low, the pins, CPU, and SFRs are initialized.

When the internal reset signal level changes from low to high,

a program is executed beginning with the address indicated by the reset vector.

Refer to 4. Special Function Registers (SFRs) for the status of the SFRs after reset.

fOCO-S

× 32

Sampling clock of

digital filter

× 4 cycles

VW0C1 bit is set to 0

(digital filter enabled)

Internal reset signal

VW0C1 bit is set to 1

(digital filter disabled)

fOCO-S

× 32

VW0C1 and VW0C7: Bits in VW0C register

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