R5F2L3ACBNFP datasheet(113/848 Pages) RENESAS

113 / 848 page

6. Voltage Detection Circuit

REJ09B0441-0010 Rev.0.10

Jul 30, 2008

Page 77 of 809

Under development Preliminary specification

Specifications in this manual are tentative and subject to change.

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,

R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

Figure 6.7

Operating Example of Voltage Monitor 2 Interrupt

Vdet2

VW1C3 bit

VCC or LVCMP2

The above applies under the following conditions:

• VCA27 bit in VCA2 register = 1 (voltage detection 2 circuit enabled)

• VW2C0 bit in VW2C register = 1 (voltage monitor 2 interrupt enabled)

Note:

1. When voltage monitor 0 reset is not used, set the power supply to VCC

≥ 1.8 V.

1.8 V (1)

Sampling clock of

digital filter

× 2 cycles

VW2C2 bit

VW2C1 bit is set to 1

(digital filter disabled),

VCAC2 bit is set to 0

(one edge),

and

VW2C7 bit is set to 0

(when VCC or LVCMP2

reaches Vdet2 or above)

VCA13: Bit in VCA1 register

VW2C1, VW2C2, VW2C3, VW2C7: Bits in VW2C register

VCAC2: Bit in VCAC register

Sampling clock of

digital filter

× 2 cycles

Set to 0 by a program.

Voltage monitor 2

interrupt request

Voltage monitor 2

interrupt request

Set to 0 when an interrupt request

is acknowledged.

VW2C2 bit

Voltage monitor 2

interrupt request

VW2C1 bit is set to 0

(digital filter enabled)

and

VCAC2 bit is set to 1

(both edges)

VW2C2 bit

Set to 0 when an interrupt request

is acknowledged.

Set to 0 by a program.

Voltage monitor 2

interrupt request

VW2C1 bit is set to 0

(digital filter enabled),

VCAC2 bit is set to 0

(one edge),

and

VW2C7 bit is set to 0

(when VCC or LVCMP2

reaches Vdet2 or above)

VW2C2 bit

Voltage monitor 2

interrupt request

VW2C1 bit is set to 0

(digital filter enabled),

VCAC2 bit is set to 0

(one edge),

and

VW2C7 bit is set to 1

(when VCC or LVCMP2

reaches Vdet2 or below)

Set to 0 by a program.

VW2C2 bit

Voltage monitor 2

interrupt request

VW2C1 bit is set to 1

(digital filter disabled)

and

VCAC2 bit is set to 1

(both edges)

Set to 0 by a program.

Set to 0 when an interrupt request

is acknowledged.

Set to 0 by a program.

Set to 0 when an interrupt request

is acknowledged.

Set to 0 by a program.

VW2C1 bit is set to 1

(digital filter disabled),

VCAC2 bit is set to 0

(one edge),

and

VW2C7 bit is set to 1

(when VCC or LVCMP2

reaches Vdet2 or below)

Set to 0 when an interrupt request

is acknowledged.

Set to 0 when an interrupt request

is acknowledged.

R5F2L3ACBNFP Datasheet(PDF) 113 Page - Renesas Technology Corp

R5F2L3ACBNFP Datasheet(HTML) 113 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL