R5F2L3ACBNFP datasheet(215/848 Pages) RENESAS

215 / 848 page

REJ09B0441-0010 Rev.0.10

Jul 30, 2008

Page 179 of 809

Under development Preliminary specification

Specifications in this manual are tentative and subject to change.

12. Interrupts

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,

R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

12.3.5

Interrupt Response Time

Figure 12.4 shows the Interrupt Response Time. The interrupt response time is the period from when an

interrupt request is generated until the first instruction in the interrupt routine is executed. The interrupt

response time includes the period from when an interrupt request is generated until the currently executing

instruction is completed (refer to (a) in Figure 12.4) and the period required for executing the interrupt sequence

(20 cycles, refer to (b) in Figure 12.4).

Figure 12.4

Interrupt Response Time

12.3.6

IPL Change when Interrupt Request is Acknowledged

When a maskable interrupt request is acknowledged, the interrupt priority level of the acknowledged interrupt

is set in the IPL.

When a software interrupt or special interrupt request is acknowledged, the level listed in Table 12.5 is set in

the IPL.

Table 12.5 lists the IPL Value When Software or Special Interrupt is Acknowledged.

Table 12.5

IPL Value When Software or Special Interrupt is Acknowledged

Interrupt Source without Interrupt Priority Level

Value Set in IPL

Watchdog timer, oscillation stop detection, voltage monitor 1/comparator A1,

voltage monitor 2/comparator A2, address break

Software, address match, single-step

No change

Interrupt request generation

Interrupt request acknowledgement

Instruction

Interrupt sequence

Instruction in

interrupt routine

Time

(a)

20 cycles (b)

Interrupt response time

(a) The period from when an interrupt request is generated until the currently executing instruction is completed.

The length of time varies depending on the instruction being executed. The DIVX instruction requires

the longest time, 30 cycles (no wait states if the divisor is a register).

(b) 21 cycles for address match and single-step interrupts.

R5F2L3ACBNFP Datasheet(PDF) 215 Page - Renesas Technology Corp

R5F2L3ACBNFP Datasheet(HTML) 215 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL