R5F2L3ACBNFP datasheet(214/848 Pages) RENESAS

214 / 848 page

REJ09B0441-0010 Rev.0.10

Jul 30, 2008

Page 178 of 809

Under development Preliminary specification

Specifications in this manual are tentative and subject to change.

12. Interrupts

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,

R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

12.3.4

Interrupt Sequence

The following describes an interrupt sequence which is performed from when an interrupt request is

acknowledged until the interrupt routine is executed.

When an interrupt request is generated while an instruction is being executed, the CPU determines its interrupt

priority level after the instruction is completed. The CPU starts the interrupt sequence from the following cycle.

However, for the SMOVB, SMOVF, SSTR, or RMPA instruction, if an interrupt request is generated while the

instruction is being executed, the MCU suspends the instruction to start the interrupt sequence. The interrupt

sequence is performed as indicated below.

Figure 12.3 shows the Time Required for Executing Interrupt Sequence.

(1) The CPU obtains interrupt information (interrupt number and interrupt request level) by reading address

00000h. The IR bit for the corresponding interrupt is set to 0 (no interrupt requested). (2)

(2) The FLG register is saved to a temporary register (1) in the CPU immediately before entering the interrupt

sequence.

(3) The I, D and U flags in the FLG register are set as follows:

The I flag is set to 0 (interrupts disabled).

The D flag is set to 0 (single-step interrupt disabled).

The U flag is set to 0 (ISP selected).

However, the U flag does not change state if an INT instruction for software interrupt number 32 to 63 is

executed.

(4) The CPU internal temporary register (1) is saved on the stack.

(5) The PC is saved on the stack.

(6) The interrupt priority level of the acknowledged interrupt is set in the IPL.

(7) The starting address of the interrupt routine set in the interrupt vector is stored in the PC.

After the interrupt sequence is completed, instructions are executed from the starting address of the interrupt

routine.

Figure 12.3

Time Required for Executing Interrupt Sequence

Notes:

1. These registers cannot be accessed by the user.

2. Refer to 12.7 Interrupts of Timer RC, Timer RD, Timer RG, Synchronous Serial Communication

Unit, I2C bus Interface, and Flash Memory (Interrupts with Multiple Interrupt Request Sources)

for the IR bit operations of the above interrupts.

678

CPU Clock

Address Bus

Data Bus

Address

0000h

Undefined

Interrupt

information

SP-2

SP-1

SP-4

SP-3

VEC

VEC+1

VEC+2

SP-2

content

SP-1

content

SP-4

content

SP-3

content

VEC

content

VEC+1

content

VEC+2

content

Note:

1. The indeterminate state depends on the instruction queue buffer.

A read cycle occurs when the instruction queue buffer is ready to accept instructions.

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