R5F2L3ACBNFP datasheet(216/848 Pages) RENESAS

216 / 848 page

REJ09B0441-0010 Rev.0.10

Jul 30, 2008

Page 180 of 809

Under development Preliminary specification

Specifications in this manual are tentative and subject to change.

12. Interrupts

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,

R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group

12.3.7

Saving Registers

In the interrupt sequence, the FLG register and PC are saved on the stack.

After an extended 16 bits, 4 high-order bits in the PC and 4 high-order (IPL) and 8 low-order bits in the FLG

Figure 12.5 shows the Stack State Before and After Acknowledgement of Interrupt Request.

The other necessary registers should be saved by a program at the beginning of the interrupt routine. The

PUSHM instruction can save several registers in the register bank being currently used (1) with a single

instruction.

Note:

1. Selectable from registers R0, R1, R2, R3, A0, A1, SB, and FB.

Figure 12.5

Stack State Before and After Acknowledgement of Interrupt Request

Stack

[SP]

SP value before

interrupt request

acknowledgement (1)

Previous stack contents

LSB

MSB

Address

Previous stack contents

−4

−3

−2

−1

m+1

Stack state before interrupt request acknowledgement

[SP]

New SP value (1)

Previous stack contents

LSB

MSB

Previous stack contents

m+1

Stack state after interrupt request acknowledgement

PCL

PCM

FLGL

FLGH

PCH

−4

−3

−2

−1

Stack

Address

PCL

: 8 low-order bits of PC

PCM

: 8 middle-order bits of PC

PCH

: 4 high-order bits of PC

FLGL

: 8 low-order bits of FLG

FLGH

: 4 high-order bits of FLG

Note:

1. When an INT instruction for software numbers 32 to 63 has been executed,

this SP is indicated by the U flag. Otherwise it is ISP.

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