AX2000-1CS896 datasheet(76/226 Pages) ACTEL

76 / 226 page

Axcelerator Family FPGAs

2- 62

v2.7

Implementation Example:

Figure 2-47 shows a complex clock distribution example. The reference clock (RefCLK) of PLLE is being sourced from

non-clock signal pins (INBUF to PLLINT). The CLK1 output of PLLE is being fed to the RefCLK input of PLLF. The CLK2

output of PLLE is driving logic (via PLLOUT). In turn, this logic is driving the global resource CLKE. PLLF is driving both

CLKF and CLKG global resources.

Figure 2-45 • Example of HCLKA driven from a PLL with External Clock Source

Figure 2-46 • Example of PLLINT and PLLOUT Usage

Figure 2-47 • Complex Clock Distribution Example

HCLKAP

HCLKAN

PLLHCLK

HCLKA

Network

CLK1

CLK2

RefCLK

PLLA

PLLINT

PLLHCLK

PLLOUT

HCLKA

Network

CLK1

CLK2

RefCLK

PLLA

Logic

CLK1

CLK2

RefCLK

PLLF

CLK1

CLK2

RefCLK

PLLE

PLLINT

INBUF

Non-Clock

Pins

PLLRCLK

PLLOUT

PLLRCLK

CLKE

Logic

CLKF

CLKG

CLKINT

AX2000-1CS896 Datasheet(PDF) 76 Page - Actel Corporation

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