AX2000-1CS896 datasheet(97/226 Pages) ACTEL

97 / 226 page

Axcelerator Family FPGAs

v2.7

2-83

The active-high CLR pin is used to reset the FIFO to the

empty state, which sets FULL and AFULL low, and EMPTY

and AEMPTY high.

Assuming that the EMPTY flag is not set, new data is

read from the FIFO when REN is valid on the active edge

of the clock. Write and read transfers are described with

timing requirements in "Timing Characteristics" on

page 2-85.

Glitch Elimination

An analog filter is added to each FIFO controller to

guarantee glitch-free FIFO-flag logic.

Overflow and Underflow Control

The counter MSB keeps track of the difference between

the read address (RA) and the write address (WA). The

EMPTY flag is set when the read and write addresses are

equal. To prevent underflow, the write address is double-

sampled by the read clock prior to comparison with the

read address (part A in Figure 2-64). To prevent overflow,

the read address is double-sampled by the write clock

prior to comparison to the write address (part B in

Figure 2-64).

FIFO Configurations

Unlike the RAM, the FIFO's write width and read width

cannot be specified independently. For the FIFO, the

write and read widths must be the same. The WIDTH pins

are used to specify one of six allowable word widths, as

shown in Table 2-95.

The DEPTH pins allow RAM cells to be cascaded to create

larger FIFOs. The four pins allow depths of 2, 4, 8, and 16

to be specified. Table 2-85 on page 2-72 describes the

FIFO depth options for various data width and memory

blocks.

Interface

Figure 2-65

shows

logic

block

diagram

the

Axcelerator FIFO module.

Cascading FIFO Blocks

FIFO blocks can be cascaded to create deeper FIFO

functions. When building larger FIFO blocks, if the word

width can be fractured in a multi-bit FIFO, the fractured

word configuration is recommended over a cascaded

configuration. For example, 256x36 can be configured as

two blocks of 256x18. This should be taken into account

when building the FIFO blocks manually. However, when

using SmartGen, the user only needs to specify the depth

and width of the necessary FIFO blocks. SmartGen

automatically

configures

these

blocks

optimize

performance.

Clock

As with RAM configuration, the RCLK and WCLK pins

have independent polarity selection

Figure 2-64 • Overflow and Underflow Control

EMPTY

RCLK

FULL

WCLK

Table 2-95 • FIFO Width Configurations

WIDTH(2:0)

W x D

000

1 x 4k

001

2 x 2k

010

4 x 1k

011

9 x 512

100

18 x 256

101

36 x 128

11x

reserved

Figure 2-65 • FIFO Block Diagram

DEPTH [3:0]

RD [35:0]

FULL

EMPTY

AFULL

AEMPTY

WIDTH [2:0]

FWEN

FREN

PIPE

RCLK

WD [35:0]

AEVAL [7:0]

AFVAL [7:0]

WCLK

CLR

AX2000-1CS896 Datasheet(PDF) 97 Page - Actel Corporation

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