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AX2000-1CS896 Datasheet(PDF) 96 Page - Actel Corporation |
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AX2000-1CS896 Datasheet(HTML) 96 Page - Actel Corporation |
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96 / 226 page ![]() Axcelerator Family FPGAs 2- 82 v2.7 Figure 2-63 illustrates flag generation. The Verilog codes for the flags are: assign AF = (DIFF[15:0] >={AFVAL[7:0],8'b00000000})?1:0; assign AE = ({AEVAL[7:0],8'b00000000}>=DIFF[15:0])?1:0; The number of DIFF-bits active depends on the configuration depth and width (Table 2-94). Figure 2-63 • ALMOST-EMPTY and ALMOST-FULL Logic Table 2-94 • Number of Available Configuration Bits Number of Blocks Block DxW Number of AEVAL/AFVAL Bits 11x1 4 21x2 4 22x1 5 41x4 4 42x2 5 44x1 6 81x8 4 82x4 5 84x2 6 88x1 7 16 1x16 4 16 2x8 5 16 4x4 6 16 8x2 7 16 16x1 8 ALMOST EMPTY and ALMOST FULL Logic WCNTR [15:0] WCLK RCNTR [15:0] RCLK 16 16 X Y X Y AEMPTY AFULL X>=Y (16 bit) DIFF [15:0] AEVAL [7:0], GND [7:0] (MSB....LSB) AFVAL [7:0], GND [7:0] (MSB....LSB) |
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