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AX2000-1CS896 Datasheet(PDF) 25 Page - Actel Corporation

Part # AX2000-1CS896
Description  Axcelerator Family FPGAs
PDF  226 Pages
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Manufacturer  ACTEL [Actel Corporation]
Direct Link  http://www.actel.com
Logo ACTEL - Actel Corporation

AX2000-1CS896 Datasheet(HTML) 25 Page - Actel Corporation

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Axcelerator Family FPGAs
v2.7
2-11
The differential amplifier supply voltage VCCDA should be
connected to 3.3V.
A user can gain access to the various I/O standards in
three ways:
•
Instantiate specific library macros that represent
the desired specific standard
•
Use generic I/O macros and then use Actel
Designer’s PinEditor to specify the desired I/O
standards (please note that this is not applicable
to differential standards)
•
A combination of the first two methods.
Please refer to the I/O Features in Axcelerator Family
Devices application note and the Antifuse Macro Library
Guide for more details.
Table 2-8 • I/O Standards Supported by the Axcelerator Family
I/O Standard
Input/Output Supply
Voltage (VCCI)
Input Reference Voltage
(VREF)
Board Termination Voltage
(VTT)
LVTTL
3.3
N/A
N/A
LVCMOS 2.5V
2.5
N/A
N/A
LVCMOS 1.8V
1.8
N/A
N/A
LVCMOS 1.5V (JDEC8-11)
1.5
N/A
N/A
3.3V PCI/PCI-X
3.3
N/A
N/A
GTL+ 3.3V
3.3
1.0
1.2
GTL+ 2.5V*
2.5
1.0
1.2
HSTL Class 1
1.5
0.75
0.75
SSTL3 Class 1 and II
3.3
1.5
1.5
SSTL2 Class1 and II
2.5
1.25
1.25
LVDS
2.5
N/A
N/A
LVPECL
3.3
N/A
N/A
Note: *2.5V GTL+ is not supported across the full military temperature range.
Table 2-9 • Supply Voltages
VCCA
VCCI
Input Tolerance
Output Drive Level
1.5V
1.5V
3.3V
1.5V
1.5V
1.8V
3.3V
1.8V
1.5V
2.5V
3.3V
2.5V
1.5V
3.3V
3.3V
3.3V
Table 2-10 • I/O Features Comparison
I/O Assignment
Clamp Diode
Hot Insertion
5V Tolerance
Input Buffer
Output Buffer
LVTTL
No
Yes
Yes1
Enabled/Disabled
3.3V PCI, 3.3V PCI-X
Yes
No
Yes1, 2
Enabled/Disabled
LVCMOS2.5V
No
Yes
No
Enabled/Disabled
LVCMOS1.8V
No
Yes
No
Enabled/Disabled
LVCMOS1.5V (JESD8-11)
No
Yes
No
Enabled/Disabled
Voltage-Referenced Input Buffer
No
Yes
No
Enabled/Disabled
Differential, LVDS/LVPECL, Input
No
Yes
No
Enabled
Disabled3
Differential, LVDS/LVPECL, Output
No
Yes
No
Disabled
Enabled4
Notes:
1. Can be implemented with an IDT bus switch.
2. Can be implemented with an external resistor.
3. The OE input of the output buffer must be deasserted permanently (handled by software).
4. The OE input of the output buffer must be asserted permanently (handled by software).



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