AX2000-1CS896 datasheet(23/226 Pages) ACTEL

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Axcelerator Family FPGAs

v2.7

2-9

I/O Specifications

Pin Descriptions

Supply Pins

GND

Ground

Low supply voltage.

VCCA

Supply Voltage

Supply

voltage

for

array

(1.5V).

See

"Operating

Conditions" on page 2-1 for more information.

VCCIBx

Supply Voltage

Supply voltage for I/Os. Bx is the I/O Bank ID – 0 to 7. See

"Operating

Conditions"

page 2-1

for

information.

VCCDA

Supply Voltage

Supply voltage for the I/O differential amplifier and JTAG

and probe interfaces. See "Operating Conditions" on

page 2-1 for more information. VCCDA should be tied to

3.3V.

VCCPLA/B/C/D/E/F/G/H Supply Voltage

PLL analog power supply (1.5V) for internal PLL. There

are eight in each device. VCCPLA supports the PLL

associated with global resource HCLKA, VCCPLB supports

the PLL associated with global resource HCLKB, etc. The

PLL analog power supply pins should be connected to

1.5V whether PLL is used or not.

VCOMPLA/B/C/D/E/F/G/HSupply Voltage

Compensation reference signals for internal PLL. There

are eight in each device. VCOMPLA supports the PLL

associated

with

global

resource

HCLKA,

VCOMPLE

supports the PLL associated with global resource CLKE,

etc. (see Figure 2-2 on page 2-9 for correct external

connection to the supply). The VCOMPLX pins should be

left floating if PLL is not used.

VPUMP

Supply Voltage (External Pump)

In the low power mode, VPUMP will be used to access an

external charge pump (if the user desires to bypass the

internal charge pump to further reduce power). The

device starts using the external charge pump when the

voltage level on VPUMP reaches VIH

1. In normal device

operation, when using the internal charge pump, VPUMP

should be tied to GND.

User-Defined Supply Pins

VREF

Supply Voltage

Reference voltage for I/O banks. VREF pins are configured

by the user from regular I/O pins; VREF pins are not in

fixed locations. There can be one or more VREF pins in an

I/O bank.

Global Pins

HCLKA/B/C/D

Dedicated (Hardwired) Clocks A, B, C

and D

These pins are the clock inputs for sequential modules or

north

PLLs.

Input levels are

compatible

with all

supported I/O standards. There is a P/N pin pair for

support of differential I/O standards. Single-ended clock

I/Os can only be assigned to the P side of a paired I/O.

This input is directly wired to each R-cell and offers clock

speeds independent of the number of R-cells being

driven.

When

the

HCLK

pins

are

unused,

recommended that they are tied to ground.

CLKE/F/G/H

Routed Clocks E, F, G, and H

These pins are clock inputs for clock distribution

networks or south PLLs. Input levels are compatible with

all supported I/O standards. There is a P/N pin pair for

support of differential I/O standards. Single-ended clock

I/Os can only be assigned to the P side of a paired I/O.

The clock input is buffered prior to clocking the R-cells.

When the CLK pins are unused, Actel recommends that

they are tied to ground.

1. When VPUMP = VIH, it shuts off the internal charge pump. See "Low Power Mode" on page 2-89.

Figure 2-2 • VCCPLX and VCOMPLX Power Supply Connect

1.5V Supply

Axcelerator Chip

0.1µf

10µf

250

VCCPLX

VCOMPLX

AX2000-1CS896 Datasheet(PDF) 23 Page - Actel Corporation

AX2000-1CS896 Datasheet(HTML) 23 Page - Actel Corporation

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