Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

Preview PDF HTML

AX2000-1CS896 Datasheet(PDF) 93 Page - Actel Corporation

Part # AX2000-1CS896
Description  Axcelerator Family FPGAs
PDF  226 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  ACTEL [Actel Corporation]
Direct Link  http://www.actel.com
Logo ACTEL - Actel Corporation

AX2000-1CS896 Datasheet(HTML) 93 Page - Actel Corporation

Back Button AX2000-1CS896 Datasheet HTML 89Page - Actel Corporation AX2000-1CS896 Datasheet HTML 90Page - Actel Corporation AX2000-1CS896 Datasheet HTML 91Page - Actel Corporation AX2000-1CS896 Datasheet HTML 92Page - Actel Corporation AX2000-1CS896 Datasheet HTML 93Page - Actel Corporation AX2000-1CS896 Datasheet HTML 94Page - Actel Corporation AX2000-1CS896 Datasheet HTML 95Page - Actel Corporation AX2000-1CS896 Datasheet HTML 96Page - Actel Corporation AX2000-1CS896 Datasheet HTML 97Page - Actel Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 93 / 226 page
background image
Axcelerator Family FPGAs
v2.7
2-79
Table 2-92 • Sixteen RAM Blocks Cascaded
Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70°C
'–2' Speed
'–1' Speed
'Std' Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Units
Write Mode
tWDASU
Write Data Setup vs. WCLK
16.54
18.84
22.15
ns
tWDAHD
Write Data Hold vs. WCLK
0.22
0.25
0.3
ns
tWADSU
Write Address Setup vs. WCLK
16.54
18.84
22.15
ns
tWADHD
Write Address Hold vs. WCLK
0.22
0.25
0.3
ns
tWENSU
Write Enable Setup vs. WCLK
16.54
18.84
22.15
ns
tWENHD
Write Enable Hold vs. WCLK
0.22
0.25
0.3
ns
tWCKH
WCLK Minimum High Pulse Width
0.98
1.11
1.31
ns
tWCLK
WCLK Minimum Low Pulse Width
17.44
19.86
23.35
ns
tWCKP
WCLK Minimum Period
34.87
39.73
46.7
ns
Read Mode
tRADSU
Read Address Setup vs. RCLK
18.13
20.65
24.27
ns
tRADHD
Read Address Hold vs. RCLK
0.00
0.00
0.00
ns
tRENSU
Read Enable Setup vs. RCLK
18.13
20.65
24.27
ns
tRENHD
Read Enable Hold vs. RCLK
0.00
0.00
0.00
ns
tRCK2RD1
RCLK-To-OUT (Pipelined)
12.71
14.48
17.03
ns
tRCK2RD2
RCLK-To-OUT (Non-Pipelined)
13.91
15.85
18.63
ns
tRCLKH
RCLK Minimum High Pulse Width
0.95
1.08
1.27
ns
tRCLKL
RCLK Minimum Low Pulse Width
18.75
21.36
25.11
ns
tRCKP
RCLK Minimum Period
37.5
42.72
50.22
ns



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com