AX2000-1CS896 datasheet(32/226 Pages) ACTEL

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Axcelerator Family FPGAs

2- 18

v2.7

User I/O Naming Conventions

Due to the complex and flexible nature of the Axcelerator family’s user I/Os, a naming scheme is used to show the

details of the I/O. The naming scheme explains to which bank an I/O belongs, as well as the pairing and pin polarity for

differential I/Os (Figure 2-7).

Figure 2-7 • I/O Bank and Dedicated Pin Layout

Figure 2-8 • General Naming Schemes

Corner4

Corner3

Corner1

I/O BANK 0

I/O BANK 5

I/O BANK 1

I/O BANK 4

Corner2

AX125

GND

CCDA

GND

CCDA

GND

CCDA

GND

CCDA

GND

CCDA

GND

CCA

GND

CCA

GND

CCA

GND

CCA

GND

CCI 2

GND

CCDA

GND

CCI 6

GND

CCI 7

GND

CCI 3

IOxxXBxFx

Fx refers to an

unimplemented feature

and can be ignored.

Bank I/D 0 through 7,

clockwise from IOB NW

P - Positive Pin/ N- Negative Pin

Pair number in the

bank, starting at 00,

clockwise from IOB NW

IO12PB1F1 is the positive pin of the thirteenth pair of the

first I/O bank (IOB NE). IO12PB1 combined

with IO12NB1 form a differential pair.

For those I/Os that can be employed

either as a user I/O or as a special

function, the following nomenclature

is used:

IOxxXBxFx/special_function_name

IOxxPB1Fx/xCLKx this pin can be configured as a clock

input or as a user I/O.

Examples:

AX2000-1CS896 Datasheet(PDF) 32 Page - Actel Corporation

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