AX2000-1CS896 datasheet(61/226 Pages) ACTEL

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Axcelerator Family FPGAs

v2.7

2-47

R-Cell

Introduction

The

R-cell,

the

sequential

logic

resource

the

Axcelerator devices, is the second logic module type in

the AX family architecture. It includes clock inputs for all

eight global resources of the Axcelerator architecture as

well as global presets and clears (Figure 2-31).

The main features of the R-cell include the following:

•

Direct connection to the adjacent logic module

through the hardwired connection DCIN. DCIN is

driven by the DCOUT of an adjacent C-cell via the

Direct-Connect routing resource, providing a

connection with less than 0.1 ns of routing delay.

•

The R-cell can be used as a standalone flip-flop. It

can be driven by any C-cell or I/O modules through

the regular routing structure (using DIN as a

routable data input). This gives the option of

using the R-Cell as a 2:1 MUXed flip-flop as well.

•

Provision of data enable-input (S0).

•

Independent active-low asynchronous clear (CLR).

•

Independent

active-low

asynchronous

preset

(PSET). If both CLR and PSET are low, CLR has

higher priority.

•

Clock can be driven by any of the following (CKP

selects clock polarity):

–

One of the four high performance hardwired

fast clocks (HCLKs)

–

One of the four routed clocks (CLKs)

–

User signals

•

Global power-on clear (GCLR) and preset (GPSET),

which drive each flip-flop on a chip-wide basis.

–

When the Global Set Fuse option in the

Designer software is unchecked (by default),

GCLR = 0 and GPSET =1 at device power-up.

When the option is checked, GCLR = 1 and

GPSET= 0. Both pins are pulled High when the

device is in user mode.

•

S0, S1, PSET, and CLR can be driven by routed

clocks CLKE/F/G/H or user signals.

•

DIN and S1 can be driven by user signals.

As with the C-cell, the configuration of the R-cell to

perform various functions is handled automatically for

the user through Actel's extensive macro library (please

see Actel’s Antifuse Macro Library Guide for a complete

listing of available AX macros).

Figure 2-31 • R-Cell

DCIN

DIN(user signals)

HCLKA/B/C/D

CLKE/F/G/H

Internal Logic

AX2000-1CS896 Datasheet(PDF) 61 Page - Actel Corporation

AX2000-1CS896 Datasheet(HTML) 61 Page - Actel Corporation

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