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AX2000-1CS896 Datasheet(PDF) 22 Page - Actel Corporation |
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AX2000-1CS896 Datasheet(HTML) 22 Page - Actel Corporation |
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22 / 226 page  Axcelerator Family FPGAs 2- 8 v2.7 Timing Model Hardwired Clock – Using LVTTL 24mA High Slew Clock I/O Routed Clock – Using LVTTL 24mA High Slew Clock I/O Note: Worst case timing data for the AX1000, –2 speed grade Figure 2-1 • Worst Case Timing Data Combinatorial Cell Combinatorial Cell Combinatorial Cell Combinatorial Cell DQ DQ DQ Y FCO + + Routed Clock Register Cell LVPECL LVPECL LVDS Register Cell Hardwired or Routed Clock Hardwired Clock I/O Module I/O Module (Registered) I/O Module (Nonregistered) I/O Module (Non- registered) I/O Module (Nonregistered) Y Buffer Module Buffer Module Buffer Module Carry Chain I/O I/O LVTTL Output Drive Strength = 4 (24mA) High Slew Rate t HCKH = 3.03 ns F MAX (external) = 350 MHz F MAX (internal) = 870 MHz t SUD = 0.23 ns t ICKLQ = 0.67 ns t DP = 1.70 ns t RD2 = 0.53 ns t DP = 1.84 ns t HCKL = 3.02 ns t RCKL = 3.08 ns t RCO = 0.67 ns t SUD = 0.23 ns t RD1 = 0.45 ns t PD = 0.74 ns t RCKL = 3.08 ns F MAX (external) = 350 MHz F MAX (internal) = 870 MHz t RCO = 0.67 ns t SUD = 0.23 ns t BPFD = 0.12 ns t PY = 1.01 ns GTL + 3.3V t OCLKY = 0.67 ns t SUD = 0.23 ns t BFPD = 0.12 ns t PD = 0.74 ns t BFPD = 0.12 ns t PDC = 0.57 ns t CCY = 0.61 ns t PY = 3.03 ns t PY = 2.28 ns t RD1 = 0.45 ns t RD2 = 0.53 ns t RD3 = 0.56 ns External Setup = (tDP + tRD2 + tSUD) – tHCKL = (1.72 + 0.53 + 0.23) – 3.02 = –0.54 ns Clock-to-Out (Pad-to-Pad) = tHCKL + tRCO + tRD1 + tPYs = 3.02 + 0.67 + 0.45 + 3.03 = 7.17 ns External Setup = (tDP + tRD2 + tSUD) – tRCKH = (1.72 + 0.53 + 0.23) – 3.13 = –0.65 ns Clock-to-Out (Pad-to-Pad) = tRCKH + tRCO + tRD1 + tPY = 3.13 + 0.67 + 0.45 + 3.03 = 7.28 ns |
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