AX2000-1CS896 datasheet(103/226 Pages) ACTEL

103 / 226 page

Axcelerator Family FPGAs

v2.7

2-89

Building RAM and FIFO Modules

RAM and FIFO modules can be generated and included

in a design in two different ways:

•

Using the SmartGen Core Generator where the

user defines the depth and width of the FIFO/

RAM, and then instantiates this block into the

design

(please

refer

Actel’s

SmartGen,

FlashROM, Analog System Builder, and Flash

Memory System Builder User’s Guide for more

information).

•

The alternative is to instantiate the RAM/FIFO

blocks manually, using inverters for polarity

control and tying all unused data bits to ground.

Other Architectural Features

Low Power Mode

Although designed for high performance, the AX

architecture also allows the user to place the device into

a low power mode. Each I/O bank in an Axcelerator

device can be configured individually, when in low

power mode, to tristate all outputs, disable inputs, or

both. The low power mode is activated by asserting the

LP pin, which is grounded in normal operation.

While in the low power mode, the device is still fully

functional and all internal logic states are preserved. This

allows a user to disable all but a few signals and operate

the part in a low-frequency, watchdog mode if desired.

Please note, if the I/O bank is not disabled, differential I/Os

belonging to the I/O bank will still consume normal

power, even when operating in the low power mode.

The Axcelerator device will resume normal operation

μs after the LP pin is pulled Low.

To further reduce power consumption, the internal

charge pump can be bypassed and an external power

supply voltage can be used instead. This saves the

internal charge-pump operating current, resulting in no

DC current draw. The Axcelerator family devices have a

dedicated "VPUMP" pin that can be used to access an

external charge pump device. In normal chip operation,

when using the internal charge pump, VPUMP should be

tied to GND. When the voltage level on VPUMP is set to

3.3V, the internal charge pump is turned off, and the

VPUMP voltage will be used as the charge pump voltage.

Adequate voltage regulation (i.e. high drive, low output

impedance, and good decoupling) should be used at

VPUMP.

In addition, any PLL in use can be powered down to

further reduce power consumption. This can be done

with the PowerDown pin driven Low. Driving this pin

High restarts the PLL with the output clock(s) being

stable once lock is restored.

JTAG

Axcelerator offers a JTAG interface that is compliant with

the IEEE 1149.1 standard. The user can employ the JTAG

interface for probing a design and performing any JTAG

Public Instructions as defined in the Table 2-102.

Interface

The interface consists of four inputs: Test Mode Select

(TMS), Test Data In (TDI), Test Clock (TCK), TAP Controller

Reset (TRST), and an output, Test Data Out (TDO). TMS,

TDI, and TRST have on-chip pull-up resistors.

TRST

TRST (Test-Logic Reset) is an active-low, asynchronous

reset signal to the TAP controller. The TRST input can be

used to reset the Test Access Port (TAP) Controller to the

TRST state. The TAP Controller can be held at this state

permanently by grounding the TRST pin. To hold the

JTAG TAP controller in the TRST state, it is recommended

to connect TRST to ground via a 1 k

Ω resistor.

There is an optional internal pull-up resistor available for

the TRST input that can be set by the user at

programming. Care should be exercised when using this

option in combination with an external tie-off to

ground.

An on-chip power-on-reset (POWRST) circuit is included.

POWRST has the same function as "TRST," but it only

occurs at power-up or during recovery from a VCCA and/

or VCCDA voltage drop.

TDO

TDO is normally tristated, and it is active only when the

TAP controller is in the "Shift_DR" state or "Shift_IR"

state. The least significant bit of the selected register (i.e.

IR or DR) is clocked out to TDO first by the falling edge of

TCK.

TAP Controller

The TAP Controller is compliant with the IEEE Standard

1149.1. It is a state machine of 16 states that controls the

Table 2-102 • JTAG Instruction Code

Instruction (IR4:IR0)

Binary Code

Extest

00000

Preload / Sample

00001

Intest

00010

USERCODE

00011

IDCODE

00100

HIGHZ

01110

CLAMP

01111

Diagnostic

10000

Reserved

All others

Bypass

11111

AX2000-1CS896 Datasheet(PDF) 103 Page - Actel Corporation

AX2000-1CS896 Datasheet(HTML) 103 Page - Actel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL