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EP2S30 Datasheet(PDF) 46 Page - Altera Corporation

Part # EP2S30
Description  Stratix II Device Family
PDF  238 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP2S30 Datasheet(HTML) 46 Page - Altera Corporation

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2–38
Altera Corporation
Stratix II Device Handbook, Volume 1
May 2007
TriMatrix Memory
Figure 2–26. M-RAM Row Unit Interface to Interconnect
Table 2–4 shows the input and output data signal connections along with
the address and control signal input connections to the row unit interfaces
(L0 to L5 and R0 to R5).
LAB
Row Interface Block
M-RAM Block
16
Up to 28
datain_a[ ]
addressa[ ]
addr_ena_a
renwe_a
byteenaA[ ]
clocken_a
clock_a
aclr_a
M-RAM Block to
LAB Row Interface
Block Interconnect Region
R4 and R24 Interconnects
C4 Interconnect
Direct Link
Interconnects
dataout_a[ ]
Up to 16



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