EP2S30 datasheet(41/238 Pages) ALTERA

41 / 238 page

Altera Corporation

2–33

May 2007

Stratix II Device Handbook, Volume 1

Stratix II Architecture

The M4K RAM blocks allow for different clocks on their inputs and

outputs. Either of the two clocks feeding the block can clock M4K RAM

block registers (renwe, address, byte enable, datain, and output registers).

Only the output register can be bypassed. The six labclk signals or local

interconnects can drive the control signals for the A and B ports of the

M4K RAM block. ALMs can also control the clock_a, clock_b,

renwe_a

, renwe_b, clr_a, clr_b, clocken_a, and clocken_b

signals, as shown in Figure 2–21.

The R4, C4, and direct link interconnects from adjacent LABs drive the

M4K RAM block local interconnect. The M4K RAM blocks can

communicate with LABs on either the left or right side through these row

resources or with LAB columns on either the right or left with the column

resources. Up to 16 direct link input connections to the M4K RAM Block

are possible from the left adjacent LABs and another 16 possible from the

right adjacent LAB. M4K RAM block outputs can also connect to left and

right LABs through direct link interconnect. Figure 2–22 shows the M4K

RAM block to logic array interface.

Figure 2–21. M4K RAM Block Control Signals

clock_b

clocken_a

clock_a

clocken_b

aclr_b

aclr_a

Dedicated

Row LAB

Clocks

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnect

renwe_b

renwe_a

EP2S30 Datasheet(PDF) 41 Page - Altera Corporation

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