EP2S30 datasheet(10/238 Pages) ALTERA

10 / 238 page

2–2

Altera Corporation

Stratix II Device Handbook, Volume 1

May 2007

Functional Description

Each Stratix II device I/O pin is fed by an I/O element (IOE) located at

the end of LAB rows and columns around the periphery of the device.

I/O pins support numerous single-ended and differential I/O standards.

Each IOE contains a bidirectional I/O buffer and six registers for

registering input, output, and output-enable signals. When used with

dedicated clocks, these registers provide exceptional performance and

interface support with external memory devices such as DDR and DDR2

SDRAM, RLDRAM II, and QDR II SRAM devices. High-speed serial

interface channels with dynamic phase alignment (DPA) support data

transfer at up to 1 Gbps using LVDS or HyperTransportTM technology I/O

standards.

Figure 2–1 shows an overview of the Stratix II device.

Figure 2–1. Stratix II Block Diagram

M512 RAM Blocks for

Dual-Port Memory, Shift

Registers, & FIFO Buffers

DSP Blocks for

Multiplication and Full

Implementation of FIR Filters

M4K RAM Blocks

for True Dual-Port

Memory & Other Embedded

Memory Functions

IOEs Support DDR, PCI, PCI-X,

SSTL-3, SSTL-2, HSTL-1, HSTL-2,

LVDS, HyperTransport & other

I/O Standards

IOEs

LABs

IOEs

LABs

IOEs

LABs

IOEs

LABs

DSP

Block

M-RAM Block

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