EP2S30 datasheet(4/238 Pages) ALTERA

4 / 238 page

1–2

Altera Corporation

Stratix II Device Handbook, Volume 1

May 2007

Features

■

Support for numerous single-ended and differential I/O standards

■

High-speed differential I/O support with DPA circuitry for 1-Gbps

performance

■

Support for high-speed networking and communications bus

standards including Parallel RapidIO, SPI-4 Phase 2 (POS-PHY

Level 4), HyperTransport™ technology, and SFI-4

■

Support for high-speed external memory, including DDR and DDR2

SDRAM, RLDRAM II, QDR II SRAM, and SDR SDRAM

■

Support for multiple intellectual property megafunctions from

Altera MegaCore® functions and Altera Megafunction Partners

Program (AMPPSM) megafunctions

■

Support for design security using configuration bitstream

encryption

■

Support for remote configuration updates

Table 1–1. Stratix II FPGA Family Features

Feature

EP2S15

EP2S30

EP2S60

EP2S90

EP2S130

EP2S180

ALMs

6,240

13,552

24,176

36,384

53,016

71,760

Adaptive look-up tables (ALUTs) (1)

12,480

27,104

48,352

72,768

106,032

143,520

Equivalent LEs (2)

15,600

33,880

60,440

90,960

132,540

179,400

M512 RAM blocks

104

202

329

488

699

930

M4K RAM blocks

144

255

408

609

768

M-RAM blocks

124

Total RAM bits

419,328

1,369,728

2,544,192

4,520,488

6,747,840

9,383,040

DSP blocks

18-bit × 18-bit multipliers (3)

144

192

252

384

Enhanced PLLs

Fast PLLs

488

Maximum user I/O pins

366

500

718

902

1,126

1,170

Notes to Table 1–1:

(1)

One ALM contains two ALUTs. The ALUT is the cell used in the Quartus® II software for logic synthesis.

(2)

This is the equivalent number of LEs in a Stratix device (four-input LUT-based architecture).

(3)

These multipliers are implemented using the DSP blocks.

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