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EP2S30 Datasheet(PDF) 84 Page - Altera Corporation |
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EP2S30 Datasheet(HTML) 84 Page - Altera Corporation |
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84 / 238 page  2–76 Altera Corporation Stratix II Device Handbook, Volume 1 May 2007 I/O Structure Figure 2–51 shows the IOE in bidirectional configuration. Figure 2–51. Stratix II IOE in Bidirectional I/O Configuration Note (1) Notes to Figure 2–51: (1) All input signals to the IOE can be inverted at the IOE. (2) The optional PCI clamp is only available on column I/O pins. CLRN/PRN DQ ENA Chip-Wide Reset OE Register CLRN/PRN DQ ENA Output Register VCCIO VCCIO PCI Clamp (2) Programmable Pull-Up Resistor Column, Row, or Local Interconnect ioe_clk[7..0] Bus-Hold Circuit OE Register tCO Delay CLRN/PRN DQ ENA Input Register Input Pin to Input Register Delay Input Pin to Logic Array Delay Drive Strength Control Open-Drain Output On-Chip Termination sclr/spreset oe clkout ce_out aclr/apreset clkin ce_in Output Pin Delay |
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