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TMS320VC5505 Datasheet(PDF) 47 Page - Texas Instruments

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Part # TMS320VC5505
Description  Fixed-Point Digital Signal Processor
PDF  141 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320VC5505 Datasheet(HTML) 47 Page - Texas Instruments

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4.2 Power Considerations
4.2.1
LDO Configuration
4.2.1.1 Analog LDO
4.3 Clock Considerations
TMS320VC5505
Fixed-Point Digital Signal Processor
www.ti.com
SPRS503A – JUNE 2009 – REVISED JULY 2009
The VC5505 provides several means of managing power consumption.
To minimize power consumption, the VC5505 divides its circuits into eight main isolated supply domains:
• ANA_LDOI (LDO and Bandgap Power Supply)
• Analog POR and PLL (V
DDA_ANA and VDDA_PLL)
• RTC (CV
DD_RTC)
• Digital Core (CV
DD)
• USB Core (USB_ V
DD1P3 and USB_VDDA1P3)
• USB PHY and USB PLL (USB_V
DDOSC, USB_VDDA3P3, and USB_VDDPLL)
• EMIF I/O (DV
DDEMIF)
• RTC I/O (DV
DDRTC)
• Rest of the I/O (DV
DDIO)
The VC5505 includes one Low-Dropout Regulator (LDO) which can be used to regulate the supplies of
the analog PLL and SAR ADC.
The ANA_LDOI pin (B12) provides the power to the Analog LDO, the bandgap reference generator, and
some I/O input pins and can range from 1.8 V to 3.6 V. The Bandgap provides accurate voltage and
current references to the POR, LDO, PLL, and SAR; therefore, for proper device operation, power must
always be applied to the ANA_LDOI pin. ANA_LDOO is regulated to 1.3 V and can optionally be used to
provide up to 3 mA to the VDDA_ANA (Power Management Voltage Supervisor and SAR VDD power inputs)
and VDDA_PLL (System PLL power input).
The system clock, which is used by the CPU and most of the DSP peripherals, is controlled by the system
clock generator. The system clock generator features a software-programmable PLL multiplier and several
dividers. The clock generator accepts an input reference clock from the CLKIN pin or the output clock of
the 32.768-KHz real-time clock (RTC) oscillator. The selection of the input reference clock is based on the
state of the CLK_SEL pin. The CLK_SEL pins is required to be statically tied high or low and cannot
change dynamically after reset.
In addition, the DSP requires a reference clock for USB applications. The USB reference clock is
generated using a dedicated on-chip oscillator with a 12-MHz external crystal connected to the USB_MXI
and USB_MXO pins.
The USB reference clock is not required if the USB peripheral is not being used. To completely disable the
USB oscillator, connect the USB_MXI pin to ground (VSS) and leave the USB_MXO pin unconnected. The
USB oscillator power pins (USB_VDDOSC and USB_VSSOSC) should also be connected to ground.
The RTC oscillator generates a clock when a 32.768-KHz crystal is connected to the RTC_XI and
RTC_XO pins. The 32.768-KHz crystal can be disabled if CLKIN is used as the clock source for the DSP.
However, when the RTC oscillator is disabled, the RTC peripheral will not operate and the RTC registers
(I/O address range 1900h – 197Fh) will not be accessible. This includes the RTC power management
register (RTCPMGT) which controls the RTCLKOUT and WAKEUP pins. To disable the RTC oscillator,
connect the RTC_XI pin to CVDDRTC and the RTC_XO pin to ground.
For more information on crystal specifications for the RTC oscillator and the USB oscillator, see
Section 6.4, External Clock Input From RTC_XI, CLKIN, and USB_MXI Pins.
Submit Documentation Feedback
Device Configuration
47



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