AT90SCR100 datasheet(218/433 Pages) ATMEL

218 / 433 page

218

TPR0327AY–SMS–30Jan09

AT90SCR100

• Bits 4 - FRZCLK : Freeze USB Clock Bit

Set to disable the PLL clock input (the ”Resume Detection” is still active). This reduces the

power consumption. Clear to enable the clock inputs.

• Bit 3 - Res : Reserved Bit

This bit is a reserved bit. The value read from this bit is always 0. Do not set this bit.

• Bit 2 - RESUME : Send USB Resume

Set this bit to generate a USB Resume on the USB bus.

Cleared by hardware when the USB Resume has been sent. Clearing by software has no effect.

• Bit 1 - RESET : Send USB Reset

Set this bit to generate a USB Reset on the USB bus.

Cleared by hardware when the USB Reset has been sent. Clearing by software has no effect.

Refer to the “USB Reset” section for more details.

• Bit 0 - SOFEN : Start Of Frame Generation ENable

Set this bit to generate SOF on the USB bus.

Clear this bit to disable the SOF generation and to leave the USB bus in Idle state.

17.7.2

UHSR - USB Host Status Register

• Bits 7..4 - Res : Reserved Bits

These bits are reserved bits. The value read from these bits is always 0. Do not set these bits.

• Bit 3 - SPEED : Speed Status Flag

Set by hardware when the controller is in FULL-SPEED mode. Cleared by hardware when the

controller is in LOW-SPEED mode.

• Bit 2..0 - Res : Reserved Bits

These bits are reserved bits. The value read from these bits is always 0. Do not set these bits.

This bit is different from PRR1.PRUSBH which avoid providing clock to the state

machine of USB Host Controller, disabling the whole controller.

Note

Bit

7654

$0099

----

SPEED

UHSR

Read/write

RRRRR

Initial value

0000

0x08

AT90SCR100 Datasheet(PDF) 218 Page - ATMEL Corporation