AT90SCR100 datasheet(216/433 Pages) ATMEL

216 / 433 page

216

TPR0327AY–SMS–30Jan09

AT90SCR100

17.5.13.2

“Autoswitch” mode

In this mode, the clear of the UPINTX.FIFOCON bit is performed automatically by hardware

each time the Pipe bank is empty. The firmware has to check if the next bank is empty or not

before reading the next data. On UPINTX.RXINI interrupt, the firmware reads a complete bank.

A new interrupt will be generated each time the current bank contains data to read.

The acknowledge of the UPINTX.RXINI interrupt is always performed by software.

17.5.13.3

CRC Error (isochronous only)

A CRC error can occur during IN stage if the USB controller detects a bad received packet. In

this situation, the STALLEDI/CRCERRI interrupt is triggered. This does not prevent the RXINI

interrupt from being triggered.

17.6

Interrupt system

Figure 17-9.

USB Host Controller Interrupt System

HWUPE

UHIEN.6

HWUPI

UHINT.6

HSOFI

UHINT.5

HSOFE

UHIEN.5

RXRSMI

UHINT.4

RXRSME

UHIEN.4

RSMEDI

UHINT.3

RSMEDE

UHIEN.3

RSTI

UHINT.2

RSTE

UHIEN.2

DDISCI

UHINT.1

DDISCE

UHIEN.1

DCONNI

UHINT.0

DCONNE

UHIEN.0

USB Host

Interrupt

AT90SCR100 Datasheet(PDF) 216 Page - ATMEL Corporation

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