H5GQ1H24AFR-R0C datasheet(116/173 Pages) HYNIX

116 / 173 page

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.0 /Nov. 2009

116

H5GQ1H24AFR

5.20. CLOCK FREQUENCY CHANGE SEQUENCE

Step 1) Wait until all commands have finished, all banks are idle.

Step 2) Send NOP or DESELECT (must meet setup/hold relative to clock while clock is changing) to

GDDR5 SGRAM for the entire sequence unless stated to do otherwise. The user must take care of refresh

requirements.

Step 3) If the new desired clock frequency is below the min frequency supported by PLL‐on mode, turn the

PLL off via an MRS command.

Step 4) Change the clock frequency and wait until clock is stabilized.

Step 5) If the new clock frequency is within the PLL on range and the PLL on state is desired, enable the

PLL via an MRS Command if it is not already enabled.

Step 6) Perform address training if required.

Step 7) Perform WCK2CK training. As defined in the WCK2CK training process, if the PLL is enabled,

then complete steps 7a and 7b:

7a) Reset the PLL by writing to the MRS register.

7b) Wait tLK clock cycles before issuing any commands to the GDDR5 SGRAM.

Step 8) Exit WCK2CK training.

Step 9) Perform READ and WRITE training, if required.

Step 10) GDDR5 SGRAM is ready for normal operation after any necessary interface training.

H5GQ1H24AFR-R0C Datasheet(PDF) 116 Page - Hynix Semiconductor