H5GQ1H24AFR-R0C datasheet(113/173 Pages) HYNIX

113 / 173 page

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.0 /Nov. 2009

113

H5GQ1H24AFR

executed with auto precharge disabled and then followed with the earliest possible PRECHARGE command that still accesses

all of the data in the burst. For write with auto precharge, the precharge period begins when tWR ends, with tWR measured as if

auto precharge was disabled. The access period starts with registration of the command and ends where the precharge period

(or tRP) begins. During the precharge period of the read with auto precharge enabled or write with auto precharge enabled

states, ACTIVE, PRECHARGE, READ and WRITE commands to the other bank may be applied. In either case, all other related

limitations apply (e.g., contention between read data and write data must be avoided).

4b. The minimum delay from a READ or WRITE command with auto precharge enabled, to a command to a different bank is

summarized below.

5. REFRESH and MODE REGISTER SET commands may only be issued when all banks are idle.

6. All states and sequences not shown are illegal or reserved.

7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and READs or

WRITEs with auto precharge disabled.

*** CL = CAS latency (CL)

BL = Burst length

WL = WRITE latency

tWTR = tWTRL if Bank Groups enabled and access to the same bank otherwise tWTR=tWTRS

Table 32 Minimum Delay Between Commands to Different Banks with Auto Precharge Enabled

From Command

To Command

Minimum delay

(with concurrent auto precharge)

WRITE

with AUTO

PRECHARGE

(WOMA)

READ or READ with AUTO PRECHARGE

[WLmrs + (BL/4)] tCK + tWTRL ***

WRITE or WRITE with AUTO PRECHARGE

(WOM/WOMA, WSM/WSMA or WDM/WDMA)

2 * tCK

PRECHARGE

1 tCK

ACTIVE

1 tCK

WRITE

with AUTO

PRECHARGE

(WDMA)

READ or READ with AUTO PRECHARGE

[WL + (BL/4)] tCK + tWTR ***

WRITE or WRITE with AUTO PRECHARGE

(WOM/WOMA, WSM/WSMA or WDM/WDMA)

2 * tCK

PRECHARGE

2 tCK

ACTIVE

2 tCK

WRITE

with AUTO

PRECHARGE

(WSMA)

READ or READ with AUTO PRECHARGE

[WL + (BL/4)] tCK + tWTR ***

WRITE or WRITE with AUTO PRECHARGE

(WOM/WOMA, WSM/WSMA or WDM/WDMA)

3 * tCK

PRECHARGE

3 tCK

ACTIVE

3 tCK

READ

with AUTO

PRECHARGE

READ or READ with AUTO PRECHARGE

2 * tCK

WRITE or WRITE with AUTO PRECHARGE

(WOM/WOMA, WSM/WSMA or WDM/ WDMA)

[CLmrs + (BL/4) + 2 ‐ WL] * tCK ***

PRECHARGE

1 tCK

ACTIVE

1 tCK

H5GQ1H24AFR-R0C Datasheet(PDF) 113 Page - Hynix Semiconductor

H5GQ1H24AFR-R0C Datasheet(HTML) 113 Page - Hynix Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL