AMPL138ZCE3 datasheet(69/268 Pages) TI

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5.2 Recommended Operating Conditions

OMAP-L138 Low-Power Applications Processor

www.ti.com

SPRS586A – JUNE 2009 – REVISED AUGUST 2009

NAME

DESCRIPTION

CONDITION

MIN

NOM

MAX

UNIT

CVDD

Core Logic Supply Voltage (variable)

1.2V operating point

1.14

1.2 or 1.26

1.32

1.1V operating point

1.05

1.1

1.16

1.0V operating point

0.95

1.0

1.05

RVDD

Internal RAM Supply Voltage

1.14

1.2 or 1.26

1.32

RTC_CVDD

RTC Core Logic Supply Voltage

1.14

1.2 or 1.26

1.32

PLL0_VDDA

PLL0 Supply Voltage

1.14

1.2 or 1.26

1.32

PLL1_VDDA

PLL1 Supply Voltage

1.14

1.2 or 1.26

1.32

SATA_VDD

SATA Core Logic Supply Voltage

1.14

1.2 or 1.26

1.32

USB_CVDD(1)

USB0, USB1 Core Logic Supply Voltage

1.14

1.2 or 1.26

1.32

USB0_VDDA18

USB0 PHY Supply Voltage

1.71

1.8

1.89

USB0_VDDA33

USB0 PHY Supply Voltage

3.15

3.3

3.45

USB1_VDDA18

USB1 IO Supply Voltage

1.71

1.8

1.89

Supply

USB1_VDDA33

USB1 IO Supply Voltage

3.15

3.3

3.45

Voltage

SATA_VDDR

SATA PHY Internal Regulator Supply Voltage

1.71

1.8

1.89

DDR_DVDD18

DDR2 PHY Supply Voltage

1.71

1.8

1.89

0.5*

0.49*

0.51*

DDR_VREF

DDR2/mDDR reference voltage

DDR_DVDD1

DDR_DVDD18

DDR2/mDDR impedance control,

DDR_ZP

Vss

connected via 50

Ω resistor to Vss

1.8V operating point

1.71

1.8

1.89

Power Group A Dual-voltage IO

DVDD3318_A

Supply Voltage

3.3V operating point

3.15

3.3

3.45

1.8V operating point

1.71

1.8

1.89

Power Group B Dual-voltage IO

DVDD3318_B

Supply Voltage

3.3V operating point

3.15

3.3

3.45

1.8V operating point

1.71

1.8

1.89

Power Group C Dual-voltage IO

DVDD3318_C

Supply Voltage

3.3V operating point

3.15

3.3

3.45

VSS

Core Logic Digital Ground

PLL0_VSSA

PLL0 Ground

PLL1_VSSA

PLL1 Ground

SATA_VSS

SATA PHY Ground

Supply

Ground

OSCVSS(2)

Oscillator Ground

RTC_VSS(2)

RTC Oscillator Ground

USB0_VSSA

USB0 PHY Ground

USB0_VSSA33

USB0 PHY Ground

VIH

High-level input voltage, Dual-voltage I/O, 3.3V(3)

High-level input voltage, Dual-voltage I/O, 1.8V (3)

0.65*DVDD

Voltage

Input High

High-level input voltage, RTC_XI

0.8*RTC_CVDD

High-level input voltage, OSCIN

0.8*CVDD

High-level input voltage, SATA_REFCLKP and

TBD

SATA_REFCLKN

VIL

Low-level input voltage, Dual-voltage I/O, 3.3V(3)

0.8

High-level input voltage, Dual-voltage I/O, 1.8V (3)

0.35*DVDD

Voltage

Input Low

Low-level input voltage, RTC_XI

0.2*RTC_CVDD

Low-level input voltage, OSCIN

0.2*CVDD

Low-level input voltage, SATA_REFCLKP and

TBD

SATA_REFCLKN

Transition

10%-90%, All Inputs (except SATA, USB0 and DDR2)

Time

(1)

This pin is an internal LDO output and connected via 0.22 F capacitor to VSS

(2)

When an external crystal is used oscillator (OSC_VSS, RTC_VSS) ground must be kept separate from other grounds and connected

directly to the crystal load capacitor ground. These pins are shorted to VSS on the device itself and should not be connected to VSS on

the circuit board. If a crystal is not used and the clock input is driven directly, then the oscillator VSS may be connected to board ground.

(3)

These IO specifications apply to the dual-voltage IOs only and do not apply to DDR2/mDDR or SATA interfaces. DDR2/mDDR IOs are

1.8V IOs and adhere to the JESD79-2A standard.

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Device Operating Conditions

AMPL138ZCE3 Datasheet(PDF) 69 Page - Texas Instruments

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