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AMPL138ZCE3 Datasheet(PDF) 19 Page - Texas Instruments |
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AMPL138ZCE3 Datasheet(HTML) 19 Page - Texas Instruments |
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19 / 268 page  3.5.2 DSP Memory Mapping 3.5.2.1 ARM Internal Memories 3.5.2.2 External Memories 3.5.2.3 DSP Internal Memories 3.5.2.4 C674x CPU OMAP-L138 Low-Power Applications Processor www.ti.com SPRS586A – JUNE 2009 – REVISED AUGUST 2009 The DSP memory map is shown in Section 3.6. By default the DSP also has access to most on and off chip memory areas, with the exception of the ARM RAM, ROM, and AINTC interrupt controller. Additionally, the DSP megamodule includes the capability to limit access to its internal memories through its SDMA port; without needing an external MPU unit. The DSP does not have access to the ARM internal memory. The DSP has access to the following External memories: • Asynchronous EMIF / SDRAM / NAND / NOR Flash (EMIFA) • SDRAM (DDR2) The DSP has access to the following DSP memories: • L2 RAM • L1P RAM • L1D RAM The C674x core uses a two-level cache-based architecture. The Level 1 Program cache (L1P) is 32 KB direct mapped cache and the Level 1 Data cache (L1D) is 32 KB 2-way set associated cache. The Level 2 memory/cache (L2) consists of a 256 KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or a combination of both. Table 3-2 shows a memory map of the C674x CPU cache registers for the device. Table 3-2. C674x Cache Registers Byte Address Register Name Register Description 0x0184 0000 L2CFG L2 Cache configuration register 0x0184 0020 L1PCFG L1P Size Cache configuration register 0x0184 0024 L1PCC L1P Freeze Mode Cache configuration register 0x0184 0040 L1DCFG L1D Size Cache configuration register 0x0184 0044 L1DCC L1D Freeze Mode Cache configuration register 0x0184 0048 - 0x0184 0FFC - Reserved 0x0184 1000 EDMAWEIGHT L2 EDMA access control register 0x0184 1004 - 0x0184 1FFC - Reserved 0x0184 2000 L2ALLOC0 L2 allocation register 0 0x0184 2004 L2ALLOC1 L2 allocation register 1 0x0184 2008 L2ALLOC2 L2 allocation register 2 0x0184 200C L2ALLOC3 L2 allocation register 3 0x0184 2010 - 0x0184 3FFF - Reserved 0x0184 4000 L2WBAR L2 writeback base address register 0x0184 4004 L2WWC L2 writeback word count register 0x0184 4010 L2WIBAR L2 writeback invalidate base address register 0x0184 4014 L2WIWC L2 writeback invalidate word count register 0x0184 4018 L2IBAR L2 invalidate base address register 0x0184 401C L2IWC L2 invalidate word count register Submit Documentation Feedback Device Overview 19 |
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