AMPL138ZCE3 datasheet(95/268 Pages) TI

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6.8.1

Power Domain and Module Topology

OMAP-L138 Low-Power Applications Processor

www.ti.com

SPRS586A – JUNE 2009 – REVISED AUGUST 2009

Table 6-9. Power and Sleep Controller (PSC) Registers (continued)

PSC0 BYTE

PSC1 BYTE

ACRONYM

ADDRESS

0x01E2 7A70

MDCTL28

Module 28 Control Register

0x01E2 7A74

MDCTL29

Module 29 Control Register

0x01E2 7A78

MDCTL30

Module 30 Control Register

0x01E2 7A7C

MDCTL31

Module 31 Control Register

The device includes two PSC modules.

Each PSC module controls clock states for several of the on chip modules, controllers and interconnect

components. Table 6-10 and Table 6-11 lists the set of peripherals/modules that are controlled by the

PSC, the power domain they are associated with, the LPSC assignment and the default (power-on reset)

module states. See the device-specific data manual for the peripherals available on a given device. The

module states and terminology are defined in Section 6.8.1.2.

Table 6-10. PSC0 Default Module Configuration

LPSC

Module Name

Power Domain

Default Module State

Auto Sleep/Wake Only

Number

EDMA3 Channel Controller 0

AlwaysON (PD0)

SwRstDisable

—

EDMA3 Transfer Controller 0

AlwaysON (PD0)

SwRstDisable

—

EDMA3 Transfer Controller 1

AlwaysON (PD0)

SwRstDisable

—

EMIFA (Br7)

AlwaysON (PD0)

SwRstDisable

—

SPI 0

AlwaysON (PD0)

SwRstDisable

—

MMC/SD 0

AlwaysON (PD0)

SwRstDisable

—

ARM Interrupt Controller

AlwaysON (PD0)

SwRstDisable

—

ARM RAM/ROM

AlwaysON (PD0)

Enable

Yes

—

UART 0

AlwaysON (PD0)

SwRstDisable

—

SCR0 (Br 0, Br 1, Br 2, Br 8)

AlwaysON (PD0)

Enable

Yes

SCR1 (Br 4)

AlwaysON (PD0)

Enable

Yes

SCR2 (Br 3, Br 5, Br 6)

AlwaysON (PD0)

Enable

Yes

PRUSS

AlwaysON (PD0)

SwRstDisable

—

ARM

AlwaysON (PD0)

SwRstDisable

—

DSP

PD_DSP (PD1)

Enable

—

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Peripheral Information and Electrical Specifications

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