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AMPL138ZCE3 Datasheet(PDF) 20 Page - Texas Instruments |
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AMPL138ZCE3 Datasheet(HTML) 20 Page - Texas Instruments |
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20 / 268 page  OMAP-L138 Low-Power Applications Processor SPRS586A – JUNE 2009 – REVISED AUGUST 2009 www.ti.com Table 3-2. C674x Cache Registers (continued) Byte Address Register Name Register Description 0x0184 4020 L1PIBAR L1P invalidate base address register 0x0184 4024 L1PIWC L1P invalidate word count register 0x0184 4030 L1DWIBAR L1D writeback invalidate base address register 0x0184 4034 L1DWIWC L1D writeback invalidate word count register 0x0184 4038 - Reserved 0x0184 4040 L1DWBAR L1D Block Writeback 0x0184 4044 L1DWWC L1D Block Writeback 0x0184 4048 L1DIBAR L1D invalidate base address register 0x0184 404C L1DIWC L1D invalidate word count register 0x0184 4050 - 0x0184 4FFF - Reserved 0x0184 5000 L2WB L2 writeback all register 0x0184 5004 L2WBINV L2 writeback invalidate all register 0x0184 5008 L2INV L2 Global Invalidate without writeback 0x0184 500C - 0x0184 5027 - Reserved 0x0184 5028 L1PINV L1P Global Invalidate 0x0184 502C - 0x0184 5039 - Reserved 0x0184 5040 L1DWB L1D Global Writeback 0x0184 5044 L1DWBINV L1D Global Writeback with Invalidate 0x0184 5048 L1DINV L1D Global Invalidate without writeback 0x0184 8000 – 0x0184 80FF MAR0 - MAR63 Reserved 0x0000 0000 – 0x3FFF FFFF Memory Attribute Registers for EMIFA SDRAM Data (CS0) 0x4000 0000 – 0x0184 8100 – 0x0184 817F MAR64 – MAR95 0x5FFF FFFF Memory Attribute Registers for EMIFA Async Data (CS2) 0x6000 0000 – 0x0184 8180 – 0x0184 8187 MAR96 - MAR97 0x61FF FFFF Memory Attribute Registers for EMIFA Async Data (CS3) 0x6200 0000 – 0x0184 8188 – 0x0184 818F MAR98 – MAR99 0x63FF FFFF Memory Attribute Registers for EMIFA Async Data (CS4) 0x6400 0000 – 0x0184 8190 – 0x0184 8197 MAR100 – MAR101 0x65FF FFFF Memory Attribute Registers for EMIFA Async Data (CS5) 0x6600 0000 – 0x0184 8198 – 0x0184 819F MAR102 – MAR103 0x67FF FFFF 0x0184 81A0 – 0x0184 81FF MAR104 – MAR127 Reserved 0x6800 0000 – 0x7FFF FFFF Memory Attribute Register for Shared RAM 0x8000 0000 – 0x8001 FFFF 0x0184 8200 MAR128 Reserved 0x8002 0000 – 0x81FF FFFF 0x0184 8204 – 0x0184 82FF MAR129 – MAR191 Reserved 0x8200 0000 – 0xBFFF FFFF Memory Attribute Registers for DDR2 Data (CS2) 0xC000 0000 – 0xDFFF 0x0184 8300 – 0x0184 837F MAR192 – MAR223 FFFF 0x0184 8380 – 0x0184 83FF MAR224 – MAR255 Reserved 0xE000 0000 – 0xFFFF FFFF See the following table for a detailed top level device memory map that includes the DSP memory space. 20 Device Overview Submit Documentation Feedback |
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