PIC16F1933-ESLASHP datasheet(330/418 Pages) MICROCHIP

330 / 418 page

PIC16F193X/LF193X

DS41364A-page 328

Preliminary

23.2

Erasing Program Memory

While executing code, program memory can only be

erased by rows. A row consists of 32 words where the

EEADRL<4:0> = 0000. To erase a row:

Load the EEADRH and EEADRL registers with

the address of new row to be erased.

Clear the CFGS bit of the EECON1 register.

Set the EEPGD bit of the EECON1 register.

Set the FREE bit of the EECON1 register.

Write 55h, then AAh, to EECON2 (Flash

programming unlock sequence).

Set control bit WR of the EECON1 register to

begin the write operation.

23.3

Writing to Flash Program Memory

Before writing, program memory should be erased

using the Erase Program Memory command.

No automatic erase occurs upon the initiation of the

write; if the program Flash needs to be erased before

writing, the row (32 words) must be erased previously.

Flash program memory may only be written to if the

destination address is in a segment of memory that is

not write-protected, as defined in bits WRT<1:0> of the

Configuration Word Register 2. Flash program memory

must be written in eight-word blocks. See Figure 23-2

for more details. A block consists of eight words with

sequential addresses, with a lower boundary defined

by an address, where EEADRL<2:0> = 000. All block

writes to program memory are done as 32-word erase

by eight-word write operations. The write operation is

edge-aligned and cannot occur across boundaries.

When the LWLO bit is ‘1’, the write sequence will only

load the buffer register and will not actually initiate the

write to program Flash:

Set the EEPGD, WREN and LWLO bits of the

EECON1 register.

Write 55h, then AAh, to EECON2 (Flash

programming unlock sequence).

Set control bit WR of the EECON1 register to

begin the write operation.

To write program data, it must first be loaded into the

buffer registers (see Figure 23-1). This is accomplished

by first writing the destination address to EEADRL and

EEADRH and then writing the data to EEDATA and

EEDATH. After the address and data have been set up,

then the following sequence of events must be executed:

Set the EEPGD control bit of the EECON1

Set the LWLO bit of the EECON1 register.

Write 55h, then AAh, to EECON2 (Flash

programming sequence).

Set the WR control bit of the EECON1 register.

Up to eight buffer register locations can be written to

with correct data. If less than eight words are being writ-

ten to in the block of eight words, then the data for the

unprogrammed words should be set to all ones.

After the “BSF EECON1,WR” instruction, the processor

requires two cycles to set up the erase/write operation.

The user must place two NOP instructions after the WR

bit is set. Since data is being written to buffer registers,

the writing of the first seven words of the block appears

to occur immediately. The processor will halt internal

operations for the typical 2 ms, only during the cycle in

which the erase takes place (i.e., the last word of the

sixteen-word block erase). This is not Sleep mode as

the clocks and peripherals will continue to run. After the

eight-word write cycle, the processor will resume oper-

ation with the third instruction after the EECON1 write

instruction.

An example of the complete eight-word write sequence

is shown in Example 23-5. The initial address is loaded

into the EEADRH and EEADRL register pair; the eight

words of data are loaded using indirect addressing.

PIC16F1933-E/P Datasheet(PDF) 330 Page - Microchip Technology

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