PIC16F1933-ESLASHP datasheet(334/418 Pages) MICROCHIP

334 / 418 page

PIC16F193X/LF193X

DS41364A-page 332

Preliminary

23.5

Write Verify

Depending on the application, good programming

practice may dictate that the value written to the data

EEPROM or program memory should be verified (see

Example 23-6) to the desired value to be written.

EXAMPLE 23-6:

WRITE VERIFY

23.5.1

USING THE DATA EEPROM

The

data

EEPROM

high-endurance,

byte

addressable array that has been optimized for the

storage of frequently changing information (e.g.,

program variables or other data that are updated often).

When variables in one section change frequently, while

variables in another section do not change, it is possible

to exceed the total number of write cycles to the

EEPROM (specification D124) without exceeding the

total number of write cycles to a single byte

(specifications D120 and D120A). If this is the case,

then a refresh of the array must be performed. For this

reason, variables that change infrequently (such as

constants, IDs, calibration, etc.) should be stored in

Flash program memory.

23.6

Protection Against Spurious Write

There are conditions when the user may not want to

write to the data EEPROM memory. To protect against

spurious EEPROM writes, various mechanisms have

been built-in. On power-up, WREN is cleared. Also, the

Power-up

Timer

(64 ms

duration)

prevents

EEPROM write.

The write initiate sequence and the WREN bit together

help prevent an accidental write during:

• Brown-out

• Power Glitch

• Software Malfunction

23.7

Data EEPROM Operation During

Code-Protect

Data memory can be code-protected by programming

the CPD bit in the Configuration Word Register 1

(Register 10-1) to ‘0’.

When the data memory is code-protected, only the

CPU is able to read and write data to the data

EEPROM. It is recommended to code-protect the

program memory when code-protecting data memory.

This prevents anyone from replacing your program with

a program that will access the contents of the data

EEPROM.

TABLE 23-2:

SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM

BANKSEL EEDATL

;

MOVF

EEDATL, W

;EEDATL not changed

;from previous write

BSF

EECON1, RD ;YES, Read the

;value written

XORWF

EEDATL, W

;

BTFSS

STATUS, Z

;Is data the same

GOTO

WRITE_ERR

;No, handle error

;Yes, continue

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

on Page

EECON1

EEPGD

CFGS

LWLO

FREE

WRERR

WREN

323

EECON2 EEPROM Control Register 2 (not a physical register)

324*

EEADRL

EEADRL7 EEADRL6 EEADRL5 EEADRL4 EEADRL3 EEADRL2 EEADRL1 EEADRL0

322

EEADRH

—

EEADRH6 EEADRH5 EEADRH4 EEADRH3 EEADRH2 EEADRH1 EEADRH0

322

EEDATL

EEDATL7 EEDATL6 EEDATL5 EEDATL4 EEDATL3 EEDATL2 EEDALT1 EEDATL0

322

EEDATH

—

EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0

322

INTCON

GIE

PEIE

TMR0IE

INTE

IOCIE

TMR0IF

INTF

IOCIF

PIE2

OSFIE

C2IE

C1IE

EEIE

BCLIE

LCDIE

—

CCP2IE

PIR2

OSFIF

C2IF

C1IF

EEIF

BCLIF

LCDIF

—

CCP2IF

Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends upon condition.

Shaded cells are not used by data EEPROM module.

Page provides register information.

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