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PIC16F1933-E/P Datasheet(PDF) 336 Page - Microchip Technology |
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PIC16F1933-E/P Datasheet(HTML) 336 Page - Microchip Technology |
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336 / 418 page  PIC16F193X/LF193X DS41364A-page 334 Preliminary © 2008 Microchip Technology Inc. 24.2 Wake-up Using Interrupts When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: • If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will not be cleared, the TO bit will not be set and the PD bit will not be cleared. • If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake-up from Sleep. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will be cleared, the TO bit will be set and the PD bit will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. FIGURE 24-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT TABLE 24-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1(1) CLKOUT(4) INT pin INTF flag (INTCON reg.) GIE bit (INTCON reg.) Instruction Flow PC Instruction Fetched Instruction Executed PC PC + 1 PC + 2 Inst(PC) = Sleep Inst(PC - 1) Inst(PC + 1) Sleep Processor in Sleep Interrupt Latency(3) Inst(PC + 2) Inst(PC + 1) Inst(0004h) Inst(0005h) Inst(0004h) Dummy Cycle PC + 2 0004h 0005h Dummy Cycle TOST(2) PC + 2 Note 1: XT, HS or LP Oscillator mode assumed. 2: TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC and RC Oscillator modes. 3: GIE = 1 assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will continue in-line. 4: CLKOUT is not available in XT, HS, or LP Oscillator modes, but shown here for timing reference. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4IOCBF3IOCBF2IOCBF1IOCBF0 104 IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 104 IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 104 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 73 PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 74 PIE2 OSFIE C2IE C1IE EEIE BCLIE LCDIE — CCP2IE 75 PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 77 PIR2 OSFIE C2IE C1IE EEIE BCLIE LCDIE — CCP2IE 78 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used in Power-down mode. |
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