ADT7462ACPZ-R7 datasheet(64/81 Pages) ONSEMI

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ADT7462

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Table 42. Register 0x0E — THERM1 Configuration Register (Note 1)

Bit

Name

R/W

Description

THERM1 Timer

Enable

R/W

Enables the THERM1 timer circuit. Default = 0.

THERM1_Local

R/W

Setting the bit to 1 means that the THERM1 pin is asserted low as an output whenever the

local temperature exceeds the local THERM1 temperature limit. Default = 0.

THERM1_

Remote 1

R/W

Setting the bit to 1 means that the THERM1 pin is asserted low as an output whenever the

Remote 1 temperature exceeds the Remote 1 THERM1 temperature limit. Default = 0.

THERM1_

Remote 2

R/W

Setting the bit to 1 means that the THERM1 pin is asserted low as an output whenever the

Remote 2 temperature exceeds the Remote 2 THERM1 temperature limit. Default = 0.

THERM1_

Remote 3

R/W

Setting the bit to 1 means that the THERM1 pin is asserted low as an output whenever the

Remote 3 temperature exceeds the Remote 3 THERM1 temperature limit. Default = 0.

[7:5]

Reserved

Reserved for future use.

1. POR = 0x00, Lock = Y, SW Reset = Y.

Table 43. Register 0x0F — THERM2 Configuration Register (Note 1)

Bit

Name

R/W

Description

THERM2

Timer Enable

R/W

Enables the THERM2 timer circuit. Default = 0.

THERM2_Local

R/W

Setting the bit to 1 means that the THERM2 pin is asserted low as an output whenever the

local temperature exceeds the local THERM2 temperature limit. Default = 0.

THERM2_

Remote 1

R/W

Setting the bit to 1 means that the THERM2 pin is asserted low as an output whenever the

Remote 1 temperature exceeds the Remote 1 THERM2 temperature limit. Default = 0.

THERM2_

Remote 2

R/W

Setting the bit to 1 means that the THERM2 pin is asserted low as an output whenever the

Remote 2 temperature exceeds the Remote 2 THERM2 temperature limit. Default = 0.

THERM2_

Remote 3

R/W

Setting the bit to 1 means that the THERM2 pin is asserted low as an output whenever the

Remote 3 temperature exceeds the Remote 3 THERM2 temperature limit. Default = 0.

[7:5]

Reserved

Reserved for future use.

1. POR = 0x00, Lock = Y, SW Reset = Y.

Table 44. Register 0x10 — Pin Configuration Register 1 (Note 1)

Bit

Name

R/W

Description

Pin 7

R/W

0 = +12V1; 1 = TACH5 input. Default =1.

Pin 4

R/W

0 = GPIO4; 1= TACH4 input (that is, if the VIDs are not selected). Default = 1.

Pin 3

R/W

0 = GPIO3; 1= TACH3 input (that is, if the VIDs are not selected). Default = 1.

Pin 2

R/W

0 = GPIO2; 1= TACH2 input (that is, if the VIDs are not selected). Default = 1.

Pin 1

R/W

0 = GPIO1; 1= TACH1 input (that is, if the VIDs are not selected). Default = 1.

Diode 3

R/W

1 enables the D3+ and D3− inputs on Pin 19 and Pin 20. 0 enables the voltage measurement

input and SCSI_TERM2 input. Default = 1.

Diode 1

R/W

1 enables the D1+ and D1− inputs on Pin 15 and Pin 16. 0 enables the voltage measurement

input and SCSI_TERM1 input. Default = 1.

VIDs

R/W

Setting this bit to 1 enables the VIDs on Pin 1 to Pin 4, Pin 28, Pin 31, and Pin 32. Default = 0.

1. POR = 0x7F, Lock = Y, SW Reset = Y.

ADT7462ACPZ-R7 Datasheet(PDF) 64 Page - ON Semiconductor

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