UJA1076 datasheet(37/47 Pages) NXP

37 / 47 page

UJA1076_2

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Product data sheet

Rev. 02 — 27 May 2010

37 of 47

NXP Semiconductors

UJA1076

High-speed CAN core system basis chip

[1]

A system reset will be performed if the watchdog is in Window mode and is triggered less than ttrig(wd)1 after the start of the watchdog

period (or in the first half of the watchdog period).

[2]

The nominal watchdog period is programmed via the NWP control bits in the WD_and_Status register (see Table 4); valid in watchdog

Window mode only.

[3]

The watchdog will be reset if it is in window mode and is triggered at least ttrig(wd)1, but not more than ttrig(wd)2, after the start of the

watchdog period (or in the second half of the watchdog period). A system reset will be performed if the watchdog is triggered more than

ttrig(wd)2 after the start of the watchdog period (watchdog overflows).

Oscillator

fosc

oscillator frequency

460.8

512

563.2

kHz

Table 11.

Dynamic characteristics …continued

Tvj = −40 °C to +150 °C; VBAT = 4.5 V to 28 V; VBAT > VV1; VBAT > VV2; R(CANH-CANL) = 45 Ω to 65 Ω; all voltages are defined

with respect to ground; positive currents flow in the IC; typical values are given at VBAT = 14 V; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Fig 15. Timing test circuit for CAN transceiver

SBC

BAT

CANL

CANH

TXDC

RCANH − RCANL

RXDC

CRXDC

GND

CCANH − CCANL

015aaa079

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