UJA1076 datasheet(14/47 Pages) NXP

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UJA1076_2

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Product data sheet

Rev. 02 — 27 May 2010

14 of 47

NXP Semiconductors

UJA1076

High-speed CAN core system basis chip

6.2.6 Int_Status register

[1]

An interrupt can be cleared by writing 1 to the relevant bit in the Int_Status register.

WSE2

R/W

WAKE2 sample enable

0: sampling continuously

1: sampling of WAKE1 is synchronized with WBIAS (sample rate controlled

by WBC)

Table 6.

Int_Control register

Bit

Symbol

Access

Power-on

default

Description

Table 7.

Int_Status register[1]

Bit

Symbol

Access

Power-on

default

Description

15:13

A2, A1, A0 R

011

R/W

access status

0: register set to read/write

1: register set to read only

V1UI

R/W

V1 undervoltage interrupts

0: no V1 undervoltage warning interrupt pending

1: V1 undervoltage warning interrupt pending

V2UI

R/W

V2 undervoltage interrupts

0: no V2 undervoltage warning interrupt pending

1: V2 undervoltage warning interrupt pending

9:8

reserved

R/W

cyclic interrupt

0: no cyclic interrupt pending

1: cyclic interrupt pending

WI1

R/W

wake-up interrupt 1

0: no wake-up interrupt 1 pending

1: wake-up interrupt 1 pending

POSI

R/W

power-on status interrupt

0: no power-on interrupt pending

1: power-on interrupt pending

WI2

R/W

wake-up interrupt 2

0: no wake-up interrupt 2 pending

1: wake-up interrupt 2 pending

CWI

R/W

CAN wake-up interrupt

0: no CAN wake-up interrupt pending

1: CAN wake-up interrupt pending

2:0

reserved

000

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