68HC705SP7 datasheet(143/230 Pages) FREESCALE

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Simple Serial Interface

SIOP Registers

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

General Release Specification

Simple Serial Interface

SPIR — Serial Peripheral Interrupt Reset

The SPIR bit is a write-only control to reset the SPIF flag bit in the

SSR. Reading the SPIR bit will return a logical zero.

1 = Reset the SPIF flag bit

0 = No effect

CPHA — Clock Phase

The CPHA bit controls the clock timing and phase in the SIOP. Data

is changed on the falling edge of SCK and data is captured (read) on

the rising edge of SCK. This bit is cleared by reset.

1 = SCK is idle low

0 = SCK is idle high

SPR0:1 — Serial Peripheral Clock Rate Selects

The SPR0 and SPR1 bits select one of four clock rates given in Table

9-1 to be supplied on the PB7/SCK pin when the device is configured

with the SIOP as a master (MSTR = 1). The fastest rate is when both

SPR0 and SPR1 are set. Both the SPR0 and SPR1 bits are cleared

by reset, which places the SIOP clock selection at the slowest rate.

Table 9-1. SIOP Clock Rate Selection

SPR1

SPR0

SIOP Clock Rate

(Oscillator Frequency

Divided by:)

Freescale Semiconductor, Inc.

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68HC705SP7 Datasheet(PDF) 143 Page - Freescale Semiconductor, Inc