SPMCK16Z4MPV20 datasheet(252/500 Pages) FREESCALE

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MULTICHANNEL COMMUNICATION INTERFACE

M68HC16 Z SERIES

10-12

USER’S MANUAL

10.3.8 Write Collision

A write collision occurs if an attempt is made to write the SPDR while a transfer is in

progress. Since the SPDR is not double buffered in the transmit direction, a successful

write to SPDR would cause data to be written directly into the SPI shift register. Be-

cause this would corrupt any transfer in progress, a write collision error is generated

instead. The transfer continues undisturbed, the data that caused the error is not writ-

ten to the shifter, and the WCOL bit in SPSR is set. No SPI interrupt is generated.

A write collision is normally a slave error because a slave has no control over when a

master initiates a transfer. Since a master is in control of the transfer, software can

avoid a write collision error generated by the master. The SPI logic can, however, de-

tect a write collision in a master as well as in a slave.

What constitutes a transfer in progress depends on the SPI configuration. For a mas-

ter, a transfer starts when data is written to the SPDR and ends when SPIF is set. For

a slave, the beginning and ending points of a transfer depend on the value of CPHA.

When CPHA = 0, the transfer begins when SS is asserted and ends when it is negated.

When CPHA = 1, a transfer begins at the edge of the first SCK cycle and ends when

SPIF is set. Refer to 10.3.4 SPI Clock Phase and Polarity Controls for more infor-

mation on transfer periods and on avoiding write collision errors.

When a write collision occurs, the WCOL bit in the SPSR is set. To clear WCOL, read

the SPSR while WCOL is set, and then either read the SPDR (either before or after

SPIF is set) or write the SPDR after SPIF is set. (Writing the SPDR before SPIF is set

results in a second write collision error.) This process clears SPIF as well as WCOL.

10.3.9 Mode Fault

When the SPI system is configured as a master and the SS input line is asserted, a

mode fault error occurs, and the MODF bit in the SPSR is set. Only an SPI master can

experience a mode fault error, caused when a second SPI device becomes a master

and selects this device as if it were a slave.

To avoid latchup caused by contention between two pin drivers, the MCU does the fol-

lowing when it detects a mode fault error:

1. Forces the MSTR control bit to zero to reconfigure the SPI as a slave.

2. Forces the SPE control bit to zero to disable the SPI system.

3. Sets the MODF status flag and generates an SPI interrupt if SPIE = 1.

4. Clears the appropriate bits in the MDDR to configure all SPI pins except the SS

pin as inputs.

After correcting the problems that led to the mode fault, clear MODF by reading the

SPSR while MODF is set and then writing to the SPCR. Control bits SPE and MSTR

may be restored to their original set state during this clearing sequence or after the

MODF bit has been cleared. Hardware does not allow the user to set the SPE and

MSTR bits while MODF is a logic one except during the proper clearing sequence.

Freescale Semiconductor, Inc.

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SPMCK16Z4MPV20 Datasheet(PDF) 252 Page - Freescale Semiconductor, Inc

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