SPMCK16Z4MPV20 datasheet(248/500 Pages) FREESCALE

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MULTICHANNEL COMMUNICATION INTERFACE

M68HC16 Z SERIES

10-8

USER’S MANUAL

Data transfer is synchronized with the internally-generated serial clock (SCK). Control

bits CPHA and CPOL in SPCR control clock phase and polarity. Combinations of

CPHA and CPOL determine the SCK edge on which the master MCU drives outgoing

data from the MOSI pin and latches incoming data from the MISO pin.

10.3.3.2 Slave Mode

Clearing the MSTR bit in SPCR selects slave mode operation. In slave mode, the SPI

is unable to initiate serial transfers. Transfers are initiated by an external bus master.

Slave mode is typically used on a multimaster SPI bus. Only one device can be bus

master (operate in master mode) at any given time.

When using the SPI in slave mode, include the following steps:

1. Write to the MMCR and interrupt registers. Refer to 10.5 MCCI Initialization for

more information.

2. Write to the MPAR to assign the following pins to the SPI: MISO, MOSI, and

SS. MISO is used for serial data output in slave mode, and MOSI is used for

serial data input. Either or both may be necessary, depending on the particular

application. SCK is the input serial clock. SS selects the SPI when asserted.

3. Write to the MDDR to direct the data flow on SPI pins. Configure the SCK,

MOSI, and SS pins as inputs. Configure MISO as an output.

4. Write to the SPCR to assign values for CPHA, CPOL, SIZE, LSBF, WOMP, and

SPIE. Set the MSTR bit to select master operation. Set the SPE bit to enable

the SPI. (The BAUD field in the SPCR of the slave device has no effect on SPI

operation.)

When SPE is set and MSTR is clear, a low state on the SS pin initiates slave mode

operation. The SS pin is used only as an input.

After a byte or word of data is transmitted, the SPI sets the SPIF flag. If the SPIE bit in

SPCR is set, an interrupt request is generated when SPIF is asserted.

Transfer is synchronized with the externally generated SCK. The CPHA and CPOL

bits determine the SCK edge on which the slave MCU latches incoming data from the

MOSI pin and drives outgoing data from the MISO pin.

10.3.4 SPI Clock Phase and Polarity Controls

Two bits in the SPCR determine SCK phase and polarity. The clock polarity (CPOL)

bit selects clock polarity (high true or low true clock). The clock phase control bit

(CPHA) selects one of two transfer formats and affects the timing of the transfer. The

clock phase and polarity should be the same for the master and slave devices. In some

cases, the phase and polarity may be changed between transfers to allow a master

device to communicate with slave devices with different requirements. The flexibility

of the SPI system allows it to be directly interfaced to almost any existing synchronous

serial peripheral.

Freescale Semiconductor, Inc.

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SPMCK16Z4MPV20 Datasheet(PDF) 248 Page - Freescale Semiconductor, Inc

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