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SPMCK16Z4MPV20 Datasheet(PDF) 391 Page - Freescale Semiconductor, Inc |
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SPMCK16Z4MPV20 Datasheet(HTML) 391 Page - Freescale Semiconductor, Inc |
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391 / 500 page  M68HC16 Z SERIES REGISTER SUMMARY USER’S MANUAL D-17 The reset state of DATA[7:3] determines whether pins controlled by CSPAR1 are ini- tially configured as high-order address lines or chip-selects. Table D-11 shows the correspondence between DATA[7:3] and the reset configuration of CS[10:6]/ ADDR[23:19]. This register may be read or written at any time. After reset, software may enable one or more pins as discrete outputs. D.2.18 Chip-Select Base Address Register Boot D.2.19 Chip-Select Base Address Registers Table D-10 CSPAR1 Pin Assignments CSPAR1 Field Chip-Select Signal Alternate Signal Discrete Output CS10PA[1:0] CS10 ADDR231 NOTES: 1. On the CPU16, ADDR[23:20] follow the logic state of ADDR19 unless externally driven. ECLK CS9PA[1:0] CS9 ADDR221 PC6 CS8PA[1:0] CS8 ADDR211 PC5 CS7PA[1:0] CS7 ADDR201 PC4 CS6PA[1:0] CS6 ADDR19 PC3 Table D-11 Reset Pin Function of CS[10:6] Data Bus Pins at Reset Chip-Select/Address Bus Pin Function DATA7 DATA6 DATA5 DATA4 DATA3 CS10/ ADDR23 CS9/ ADDR22 CS8/ ADDR21 CS7/ ADDR20 CS6/ ADDR19 11111 CS10 CS9 CS8 CS7 CS6 1111 0 CS10 CS9 CS8 CS7 ADDR19 111 0X CS10 CS9 CS8 ADDR20 ADDR19 11 0X X CS10 CS9 ADDR21 ADDR20 ADDR19 1 0X X X CS10 ADDR22 ADDR21 ADDR20 ADDR19 0X X X X ADDR23 ADDR22 ADDR21 ADDR20 ADDR19 CSBARBT — Chip-Select Base Address Register Boot $YFFA48 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR 23 ADDR 22 ADDR 21 ADDR 20 ADDR 19 ADDR 18 ADDR 17 ADDR 16 ADDR 15 ADDR 14 ADDR 13 ADDR 12 ADDR 11 BLKSZ[2:0] RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 CSBAR[0:10] — Chip-Select Base Address Registers $YFFA4C–$YFFA74 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR 23 ADDR 22 ADDR 21 ADDR 20 ADDR 19 ADDR 18 ADDR 17 ADDR 16 ADDR 15 ADDR 14 ADDR 13 ADDR 12 ADDR 11 BLKSZ[2:0] RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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