SPMCK16Z4MPV20 datasheet(395/500 Pages) FREESCALE

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M68HC16 Z SERIES

USER’S MANUAL

D-21

SPACE[1:0] — Address Space Select

Use this option field to select an address space for chip-select assertion or to configure

a chip-select as an interrupt acknowledge strobe for an external device. The CPU16

normally operates in supervisor mode only, but interrupt acknowledge cycles take

place in CPU space. Table D-17 shows address space bit encodings.

IPL[2:0] — Interrupt Priority Level

When SPACE[1:0] is set for CPU space (%00), chip-select logic can be used as an

interrupt acknowledge strobe for an external device. During an interrupt acknowledge

cycle, the interrupt priority level is driven on address lines ADDR[3:1] and is then com-

pared to the value in IPL[2:0]. If the values match, an interrupt acknowledge strobe will

be generated on the particular chip-select pin, provided other option register condi-

tions are met. Table D-18 shows IPL[2:0] field encoding.

AVEC — Autovector Enable

This field selects one of two methods of acquiring an interrupt vector during an inter-

rupt acknowledge cycle. This field is not applicable when SPACE[1:0] = %00.

0 = External interrupt vector enabled

1 = Autovector enabled

If the chip select is configured to trigger on an interrupt acknowledge cycle

(SPACE[1:0] = %00) and the AVEC field is set to one, the chip-select automatically

generates AVEC and completes the interrupt acknowledge cycle. Otherwise, the vec-

tor must be supplied by the requesting external device to complete the IACK read

cycle.

Table D-17 Address Space Bit Encodings

SPACE[1:0]

Address Space

CPU Space

User Space

Supervisor Space

Supervisor/User Space

Table D-18 Interrupt Priority Level Field Encoding

IPL[2:0]

Interrupt Priority Level

000

Any Level1

NOTES:

1. Any level means that chip-select is assert-

ed regardless of the level of the interrupt

acknowledge cycle.

001

010

011

100

101

110

111

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