SPMCK16Z4MPV20 datasheet(410/500 Pages) FREESCALE

410 / 500 page

M68HC16 Z SERIES

D-36

USER’S MANUAL

D.5.6 ADC Status Register

ADCSTAT contains information related to the status of a conversion sequence.

SCF — Sequence Complete Flag

0 = Sequence not complete

1 = Sequence complete

SCF is set at the end of the conversion sequence when SCAN is cleared, and at the

end of the first conversion sequence when SCAN is set. SCF is cleared when ADCTL1

is written and a new conversion sequence begins.

CCTR[2:0] — Conversion Counter

This field reflects the contents of the conversion counter pointer in either four or eight

count conversion sequence. The value corresponds to the number of the next result

CCF[7:0] — Conversion Complete Flags

Each bit in this field corresponds to an A/D result register (for example, CCF7 to

RSLT7). A bit is set when conversion for the corresponding channel is complete, and

remains set until the associated result register is read.

D.5.7 Right Justified, Unsigned Result Register

Conversion result is unsigned right-justified data. Bits [9:0] are used for 10-bit resolu-

tion. For 8-bit conversions, bits [7:0] contain data and bits [9:8] are zero. Bits [15:10]

always return zero when read.

D.5.8 Left Justified, Signed Result Register

Conversion result is signed left-justified data. Bits [15:6] are used for 10-bit resolution.

For 8-bit conversions, bits [15:8] contain data and bits [7:6] are zero. Although the ADC

is unipolar, it is assumed that the zero point is halfway between low and high reference

when this format is used (VRH –VRL/2). For positive input, bit 15 = 0. For negative in-

put, bit 15 = 1. Bits [5:0] always return zero when read.

ADCSTAT — ADC Status Register

$YFF70E

SCF

NOT USED

CCTR[2:0]

CCF[7:0]

RESET:

RJURR — Right-Justified, Unsigned Result Register

$YFF710–$YFF71F

NOT USED

8/10

LJSRR — Left Justified, Signed Result Register

$YFF720–$YFF72F

8/10

NOT USED

Freescale Semiconductor, Inc.

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