SPMCK16Z4MPV20 datasheet(413/500 Pages) FREESCALE

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M68HC16 Z SERIES

USER’S MANUAL

D-39

STOP — Low-Power Stop Mode Enable

0 = QSM clock operates normally.

1 = QSM clock is stopped.

When STOP is set, the QSM enters low-power stop mode. The system clock input to

the module is disabled. While STOP is set, only QSMCR reads and writes are guar-

anteed to be valid, but only writes to the QSPI RAM and other QSM registers are guar-

anteed valid. The SCI receiver and transmitter and the QSPI should be disabled

before STOP is set. To stop the QSPI, set the HALT bit in SPCR3, wait until the HAL-

TA flag is set, then set STOP. To stop the SCI, clear the TS and RE bits in SCCR1.

FRZ1 — FREEZE Assertion Response

FRZ1 determines what action is taken by the QSPI when the IMB FREEZE signal is

asserted.

0 = Ignore the IMB FREEZE signal.

1 = Halt the QSPI on a transfer boundary.

FRZ0 — Not Implemented

Bits [12:8] — Not Implemented

SUPV — Supervisor/Unrestricted

This bit has no effect because the CPU16 in the MCU operates only in supervisor

mode.

Bits [6:4] — Not Implemented

IARB[3:0] — Interrupt Arbitration ID

The IARB field is used to arbitrate between simultaneous interrupt requests of the

same priority. Each module that can generate interrupt requests must be assigned a

unique, non-zero IARB field value in order to request an interrupt.

D.6.2 QSM Test Register

QTEST — QSM Test Register

$YFFC02

Used for factory test only.

D.6.3 QSM Interrupt Level Register/Interrupt Vector Register

The values of ILQSPI[2:0] and ILSCI[2:0] in QILR determine the priority of QSPI and

SCI interrupt requests. QIVR determines the value of the interrupt vector number the

QSM supplies when it responds to an interrupt acknowledge cycle.

QILR — QSM Interrupt Levels Register

$YFFC04

QIVR — QSM Interrupt Vector Register

$YFFC05

NOT USED

ILQSPI[2:0]

ILSCI[2:0]

INTV[7:0]

RESET:

Freescale Semiconductor, Inc.

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