SPMCK16Z4MPV20 datasheet(417/500 Pages) FREESCALE

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M68HC16 Z SERIES

USER’S MANUAL

D-43

D.6.6 SCI Status Register

SCSR contains flags that show SCI operating conditions. These flags are cleared ei-

ther by SCI hardware or by a read/write sequence. The sequence consists of reading

SCSR, then reading or writing SCDR.

If an internal SCI signal for setting a status bit comes after reading the asserted status

bits, but before writing or reading SCDR, the newly set status bit is not cleared. SCSR

must be read again with the bit set and SCDR must be read or written before the status

bit is cleared.

A long-word read can consecutively access both SCSR and SCDR. This action clears

receive status flag bits that were set at the time of the read, but does not clear TDRE

or TC flags. Reading either byte of SCSR causes all 16 bits to be accessed, and any

status bit already set in either byte is cleared on a subsequent read or write of SCDR.

Bits [15:9] — Not implemented

TDRE — Transmit Data Register Empty

0 = Transmit data register still contains data to be sent to the transmit serial shifter.

1 = A new character can now be written to the transmit data register.

TC — Transmit Complete

0 = SCI transmitter is busy.

1 = SCI transmitter is idle.

RDRF — Receive Data Register Full

0 = Receive data register is empty or contains previously read data.

1 = Receive data register contains new data.

RAF — Receiver Active

0 = SCI receiver is idle.

1 = SCI receiver is busy.

IDLE — Idle-Line Detected

0 = SCI receiver did not detect an idle-line condition.

1 = SCI receiver detected an idle-line condition.

OR — Overrun Error

0 = Receive data register is empty and can accept data from the receive serial

shifter.

1 = Receive data register is full and cannot accept data from the receive serial

shifter. Any data in the shifter is lost and RDRF remains set.

SCSR — SCI Status Register

$YFFC0C

NOT USED

TDRE

RDRF

RAF

IDLE

RESET:

Freescale Semiconductor, Inc.

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