SPMCK16Z4MPV20 datasheet(418/500 Pages) FREESCALE

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M68HC16 Z SERIES

D-44

USER’S MANUAL

NF — Noise Error

0 = No noise detected in the received data.

1 = Noise detected in the received data.

FE — Framing Error

0 = No framing error detected in the received data.

1 = Framing error or break detected in the received data.

PF — Parity Error

0 = No parity error detected in the received data.

1 = Parity error detected in the received data.

D.6.7 SCI Data Register

SCDR consists of two data registers located at the same address. The receive data

terface. Data comes into the receive serial shifter and is transferred to RDR. The trans-

mit data register (TDR) is a write-only register that contains data to be transmitted.

Data is first written to TDR, then transferred to the transmit serial shifter, where addi-

tional format bits are added before transmission. R[7:0]/T[7:0] contain either the first

eight data bits received when SCDR is read, or the first eight data bits to be transmitted

when SCDR is written. R8/T8 are used when the SCI is configured for nine-bit opera-

tion. When the SCI is configured for 8-bit operation, R8/T8 has no meaning or effect.

D.6.8 Port QS Data Register

PORTQS latches I/O data. Writes drive pins defined as outputs. Reads return data

present on the pins. To avoid driving undefined data, first write a byte to PORTQS,

then configure DDRQS.

SCDR — SCI Data Register

$YFFC0E

NOT USED

R8/T8

R7/T7

R6/T6

R5/T5

R4/T4

R3/T3

R2/T2

R1/T1

R0/T0

RESET:

PORTQS — Port QS Data Register

$YFFC14

NOT USED

PQS7

PQS6

PQS5

PQS4

PQS3

PQS2

PQS1

PQS0

RESET:

Freescale Semiconductor, Inc.

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