SPMCK16Z4MPV20 datasheet(422/500 Pages) FREESCALE

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M68HC16 Z SERIES

D-48

USER’S MANUAL

SPBR[7:0] — Serial Clock Baud Rate

The QSPI uses a modulus counter to derive the SCK baud rate from the MCU system

clock. Baud rate is selected by writing a value from two to 255 into SPBR[7:0]. The

following equation determines the SCK baud rate:

Giving SPBR[7:0] a value of zero or one disables the baud rate generator. SCK is dis-

abled and assumes its inactive state value. No serial transfers occur. At reset, the SCK

baud rate is initialized to one-eighth of the system clock frequency. SPBR has 254 ac-

tive values. Table D-36 lists several possible baud values and the corresponding SCK

frequency based on a 16.78-MHz system clock.

D.6.11 QSPI Control Register 1

SPCR1 enables the QSPI and specifies transfer delays. SPCR1 must be written last

during initialization because it contains SPE. Writing a new value to SPCR1 while the

QSPI is enabled disrupts operation.

SPE — QSPI Enable

0 = QSPI is disabled. QSPI pins can be used for general-purpose I/O.

1 = QSPI is enabled. Pins allocated by PQSPAR are controlled by the QSPI.

Table D-36 Examples of SCK Frequencies

fsys

Required

Division Ratio

Value of SPBR

Actual SCK

Frequency

16.78 MHz

4.19 MHz

2.10 MHz

1.05 MHz

493 kHz

168

100 kHz

510

255

33 kHz

SPCR1 — QSPI Control Register 1

$YFFC1A

SPE

DSCKL[6:0]

DTL[7:0]

RESET:

SCK Baud Rate

sys

SPBR[7:0]

-------------------------------------

SPBR[7:0]

sys

SCK

Baud Rate Desired

--------------------------------------------------------------------------

Freescale Semiconductor, Inc.

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